[PATCH] D31783: Move size and alignment information of regclass to TargetRegisterInfo

[Krzysztof Parzyszek via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL301221: Move size and alignment information of regclass to TargetRegisterInfo (authored by kparzysz).

Changed prior to commit:
  https://reviews.llvm.org/D31783?vs=94817&id=96442#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D31783

Files:
  llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
  llvm/trunk/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
  llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp
  llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp
  llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
  llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
  llvm/trunk/lib/CodeGen/RegAllocFast.cpp
  llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
  llvm/trunk/lib/CodeGen/StackMaps.cpp
  llvm/trunk/lib/CodeGen/TargetInstrInfo.cpp
  llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
  llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp
  llvm/trunk/lib/CodeGen/VirtRegMap.cpp
  llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp
  llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp
  llvm/trunk/lib/Target/AVR/AVRFrameLowering.cpp
  llvm/trunk/lib/Target/Hexagon/BitTracker.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
  llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
  llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
  llvm/trunk/lib/Target/Mips/MipsMachineFunction.cpp
  llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
  llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
  llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.cpp
  llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
  llvm/trunk/lib/Target/X86/X86FastISel.cpp
  llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
  llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
  llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
  llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp
  llvm/trunk/lib/Target/XCore/XCoreMachineFunctionInfo.cpp

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