[PATCH] D32345: AMDGPU: Fix crash when scheduling non-memory SMRD instructions
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Mon Apr 24 10:06:47 PDT 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL301191: AMDGPU: Fix crash when scheduling non-memory SMRD instructions (authored by nha).
Changed prior to commit:
https://reviews.llvm.org/D32345?vs=96119&id=96414#toc
Repository:
rL LLVM
https://reviews.llvm.org/D32345
Files:
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/readcyclecounter.ll
Index: llvm/trunk/test/CodeGen/AMDGPU/readcyclecounter.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/readcyclecounter.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/readcyclecounter.ll
@@ -22,4 +22,18 @@
ret void
}
+; This test used to crash in ScheduleDAG.
+;
+; GCN-LABEL: {{^}}test_readcyclecounter_smem:
+; SI-DAG: s_memtime
+; VI-DAG: s_memrealtime
+; GCN-DAG: s_load_dword
+define amdgpu_cs i32 @test_readcyclecounter_smem(i64 addrspace(2)* inreg %in) #0 {
+ %cycle0 = call i64 @llvm.readcyclecounter()
+ %in.v = load i64, i64 addrspace(2)* %in
+ %r.64 = add i64 %cycle0, %in.v
+ %r.32 = trunc i64 %r.64 to i32
+ ret i32 %r.32
+}
+
attributes #0 = { nounwind }
Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -138,6 +138,11 @@
}
if (isSMRD(Opc0) && isSMRD(Opc1)) {
+ // Skip time and cache invalidation instructions.
+ if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
+ AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
+ return false;
+
assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
// Check base reg.
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