[llvm] r301191 - AMDGPU: Fix crash when scheduling non-memory SMRD instructions
Nicolai Haehnle via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 24 09:53:53 PDT 2017
Author: nha
Date: Mon Apr 24 11:53:52 2017
New Revision: 301191
URL: http://llvm.org/viewvc/llvm-project?rev=301191&view=rev
Log:
AMDGPU: Fix crash when scheduling non-memory SMRD instructions
Summary: Fixes piglit spec/arb_shader_clock/execution/*
Reviewers: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D32345
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/readcyclecounter.ll
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=301191&r1=301190&r2=301191&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Mon Apr 24 11:53:52 2017
@@ -138,6 +138,11 @@ bool SIInstrInfo::areLoadsFromSameBasePt
}
if (isSMRD(Opc0) && isSMRD(Opc1)) {
+ // Skip time and cache invalidation instructions.
+ if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
+ AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
+ return false;
+
assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
// Check base reg.
Modified: llvm/trunk/test/CodeGen/AMDGPU/readcyclecounter.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/readcyclecounter.ll?rev=301191&r1=301190&r2=301191&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/readcyclecounter.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/readcyclecounter.ll Mon Apr 24 11:53:52 2017
@@ -22,4 +22,18 @@ define amdgpu_kernel void @test_readcycl
ret void
}
+; This test used to crash in ScheduleDAG.
+;
+; GCN-LABEL: {{^}}test_readcyclecounter_smem:
+; SI-DAG: s_memtime
+; VI-DAG: s_memrealtime
+; GCN-DAG: s_load_dword
+define amdgpu_cs i32 @test_readcyclecounter_smem(i64 addrspace(2)* inreg %in) #0 {
+ %cycle0 = call i64 @llvm.readcyclecounter()
+ %in.v = load i64, i64 addrspace(2)* %in
+ %r.64 = add i64 %cycle0, %in.v
+ %r.32 = trunc i64 %r.64 to i32
+ ret i32 %r.32
+}
+
attributes #0 = { nounwind }
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