[llvm] r300984 - [AArch64][Falkor] Refine resource needs of STRQ with register offset.

[Chad Rosier via llvm-commits]

Author: mcrosier
Date: Fri Apr 21 09:33:13 2017
New Revision: 300984

URL: http://llvm.org/viewvc/llvm-project?rev=300984&view=rev
Log:
[AArch64][Falkor] Refine resource needs of STRQ with register offset.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td?rev=300984&r1=300983&r2=300984&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td Fri Apr 21 09:33:13 2017
@@ -328,6 +328,7 @@ def : InstRW<[FalkorWr_5VXVY_7cyc],   (i
 // -----------------------------------------------------------------------------
 def : InstRW<[WriteVST],              (instregex "^STP(D|S)(i)$")>;
 def : InstRW<[WriteVST, WriteAdr],    (instregex "^STP(D|S)(post|pre)$")>;
+def : InstRW<[FalkorWr_2XYZ_2ST_2VSD_0cyc], (instregex "^STRQro(W|X)$")>;
 
 def : InstRW<[WriteVST],                                                        (instregex "^ST1(One(v8b|v4h|v2s|v1d)(_POST)?|(i8|i16|i32|i64)(_POST)?|One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))$")>;
 def : InstRW<[WriteVST],                                                        (instregex "^ST2(Two(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64))$")>;

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td?rev=300984&r1=300983&r2=300984&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td Fri Apr 21 09:33:13 2017
@@ -305,6 +305,13 @@ def FalkorWr_2LD_2VXVY_2none_4cyc: Sched
   let NumMicroOps = 6;
 }
 
+def FalkorWr_2XYZ_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST,
+                                                FalkorUnitVSD, FalkorUnitXYZ,
+                                                FalkorUnitST, FalkorUnitVSD]> {
+  let Latency = 0;
+  let NumMicroOps = 6;
+}
+
 //===----------------------------------------------------------------------===//
 // Define 8 micro-op types