[llvm] r300951 - [Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing `Uses = [CPSR]`

Artyom Skrobov via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 21 00:35:23 PDT 2017


Author: askrobov
Date: Fri Apr 21 02:35:21 2017
New Revision: 300951

URL: http://llvm.org/viewvc/llvm-project?rev=300951&view=rev
Log:
[Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing `Uses = [CPSR]`

Summary: Thanks to Oliver Stannard for helping catch this.

Reviewers: olista01, efriedma

Subscribers: llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D31815

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/test/CodeGen/Thumb/long.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=300951&r1=300950&r2=300951&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Apr 21 02:35:21 2017
@@ -953,7 +953,7 @@ let isAdd = 1 in {
   /// These opcodes will be converted to the real non-S opcodes by
   /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
   let hasPostISelHook = 1, Defs = [CPSR] in {
-    let isCommutable = 1 in
+    let isCommutable = 1, Uses = [CPSR] in
     def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                             2, IIC_iALUr,
                             [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
@@ -1292,6 +1292,7 @@ def tSUBrr :                    // A8.6.
 /// These opcodes will be converted to the real non-S opcodes by
 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
 let hasPostISelHook = 1, Defs = [CPSR] in {
+  let Uses = [CPSR] in
   def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
                           2, IIC_iALUr,
                           [(set tGPR:$Rdn, CPSR, (ARMsube tGPR:$Rn, tGPR:$Rm,

Modified: llvm/trunk/test/CodeGen/Thumb/long.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/long.ll?rev=300951&r1=300950&r2=300951&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/long.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/long.ll Fri Apr 21 02:35:21 2017
@@ -206,3 +206,34 @@ entry:
 ; CHECK: adds r0, r0, r2
 ; CHECK: sbcs r1, r3
 }
+
+declare void @f13(i64 %x)
+
+define void @f14(i1 %x, i64 %y) #0 {
+; CHECK-LABEL: f14:
+entry:
+  %a = add i64 %y, 47
+  call void @f13(i64 %a)
+; CHECK: bl
+  br i1 %x, label %if.end, label %if.then
+
+if.then:
+  call void @f13(i64 %y)
+; CHECK: bl
+  br label %if.end
+
+if.end:
+  %b = add i64 %y, 45
+  call void @f13(i64 %b)
+; CHECK: adds
+; CHECK: adcs
+; CHECK: bl
+  %c = add i64 %y, 47
+  call void @f13(i64 %c)
+; CHECK: adds
+; CHECK-NEXT: adcs
+; CHECK: bl
+  ret void
+}
+
+attributes #0 = { optsize }




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