[llvm] r300904 - ARM: lower "fence singlethread" to a pure compiler barrier.

[Tim Northover via llvm-commits]

Author: tnorthover
Date: Thu Apr 20 16:56:52 2017
New Revision: 300904

URL: http://llvm.org/viewvc/llvm-project?rev=300904&view=rev
Log:
ARM: lower "fence singlethread" to a pure compiler barrier.

Single-threaded fences aren't required to provide any synchronization with
other processing elements so there's no need for a DMB. They should still be a
barrier for compiler optimizations though.

Added:
    llvm/trunk/test/CodeGen/ARM/fence-singlethread.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=300904&r1=300903&r2=300904&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Apr 20 16:56:52 2017
@@ -3358,8 +3358,12 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHA
 
 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
                                  const ARMSubtarget *Subtarget) {
-  // FIXME: handle "fence singlethread" more efficiently.
   SDLoc dl(Op);
+  ConstantSDNode *ScopeN = cast<ConstantSDNode>(Op.getOperand(2));
+  auto Scope = static_cast<SynchronizationScope>(ScopeN->getZExtValue());
+  if (Scope == SynchronizationScope::SingleThread)
+    return Op;
+
   if (!Subtarget->hasDataBarrier()) {
     // Some ARMv6 cpus can support data barriers with an mcr instruction.
     // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=300904&r1=300903&r2=300904&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Apr 20 16:56:52 2017
@@ -5975,3 +5975,10 @@ def CMP_SWAP_64 : PseudoInst<(outs GPRPa
                              (ins GPR:$addr, GPRPair:$desired, GPRPair:$new),
                              NoItinerary, []>, Sched<[]>;
 }
+
+def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary,
+                                 [(atomic_fence imm:$ordering, 0)]> {
+  let hasSideEffects = 1;
+  let Size = 0;
+  let AsmString = "@ COMPILER BARRIER";
+}

Added: llvm/trunk/test/CodeGen/ARM/fence-singlethread.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fence-singlethread.ll?rev=300904&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fence-singlethread.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/fence-singlethread.ll Thu Apr 20 16:56:52 2017
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv7-apple-ios %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -filetype=obj -o %t
+; RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=OBJ
+
+; OBJ-NOT: dmb
+
+define void @fence_singlethread() {
+; CHECK-LABEL: fence_singlethread:
+; CHECK-NOT: dmb
+; CHECK: @ COMPILER BARRIER
+; CHECK-NOT: dmb
+
+  fence singlethread seq_cst
+  ret void
+}