[PATCH] D32229: [globalisel][tablegen] Add support for RegisterOperand.

[Daniel Sanders via Phabricator via llvm-commits]

dsanders created this revision.
Herald added subscribers: igorb, dberris.

It functions just like RegisterClass except that the class is obtained
from a field.

Depends on https://reviews.llvm.org/D31761.


https://reviews.llvm.org/D32229

Files:
  test/TableGen/GlobalISelEmitter.td
  utils/TableGen/GlobalISelEmitter.cpp


Index: utils/TableGen/GlobalISelEmitter.cpp
===================================================================
--- utils/TableGen/GlobalISelEmitter.cpp
+++ utils/TableGen/GlobalISelEmitter.cpp
@@ -1383,6 +1383,12 @@
       return Error::success();
     }
 
+    if (ChildRec->isSubClassOf("RegisterOperand")) {
+      OM.addPredicate<RegisterBankOperandMatcher>(
+          Target.getRegisterClass(ChildRec->getValueAsDef("RegClass")));
+      return Error::success();
+    }
+
     // Check for ComplexPattern's.
     if (ChildRec->isSubClassOf("ComplexPattern")) {
       const auto &ComplexPattern = ComplexPatternEquivs.find(ChildRec);
@@ -1446,7 +1452,8 @@
       return Error::success();
     }
 
-    if (ChildRec->isSubClassOf("RegisterClass")) {
+    if (ChildRec->isSubClassOf("RegisterClass") ||
+        ChildRec->isSubClassOf("RegisterOperand")) {
       DstMIBuilder.addRenderer<CopyRenderer>(InsnMatcher, DstChild->getName());
       return Error::success();
     }
@@ -1613,6 +1620,8 @@
 
     const auto &DstIOperand = DstI.Operands[OpIdx];
     Record *DstIOpRec = DstIOperand.Rec;
+    if (DstIOpRec->isSubClassOf("RegisterOperand"))
+      DstIOpRec = DstIOpRec->getValueAsDef("RegClass");
     if (!DstIOpRec->isSubClassOf("RegisterClass"))
       return failedImport("Dst MI def isn't a register class");
 
Index: test/TableGen/GlobalISelEmitter.td
===================================================================
--- test/TableGen/GlobalISelEmitter.td
+++ test/TableGen/GlobalISelEmitter.td
@@ -9,6 +9,7 @@
 
 def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
+def GPR32Op : RegisterOperand<GPR32>;
 
 class I<dag OOps, dag IOps, list<dag> Pat>
   : Instruction {
@@ -91,7 +92,7 @@
 // CHECK-NEXT:        }
 
 def : GINodeEquiv<G_SELECT, select>;
-def INSN2 : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2, complex:$src3), []>;
+def INSN2 : I<(outs GPR32:$dst), (ins GPR32Op:$src1, complex:$src2, complex:$src3), []>;
 def : Pat<(select GPR32:$src1, complex:$src2, complex:$src3),
           (INSN2 GPR32:$src1, complex:$src3, complex:$src2)>;
 


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