[PATCH] D31396: [X86][LLVM][Canonical Compare Intrinsics] Creating a canonical representation for X86 CMP intrinsics

[Zvi Rackover via Phabricator via llvm-commits]

zvi added a comment.

In https://reviews.llvm.org/D31396#724945, @craig.topper wrote:

> What is the plan for supporting the SSE intrinsics?
>
> What does this canonicalization enable if we can't properly do it for the SSE intrinsics? Are we getting worse codegen for the scalar and 128-bit intrinsics on AVX targets just because we can't know we're an AVX target in InstCombine?


IIUC, the issue here is that @llvm.x86.sse.cmp.* instrinsics function calls can be lowered to either SSE encoded instructions or to AVX instructions. The difference in not only in the encoding, but also in the possible predicates the instructions support.
The SSE variants support 8 predicates and the AVX variants support a richer set of 32 variants.
The concern is that at InstCombine-time we don't have knowledge about what subtarget features will be enabled so we can't replace an SSE immediate with an AVX-only immediate because if we end-up lowering to an SSE target, we don't expect (or at least now it doesn't) the backend to reverse back to an SSE-legal form.
But what if the function contains "target-cpu" or "target-features" attributes which will allow us to assume these will be used by the backend? would it be ok then to perform the canonicalization?


https://reviews.llvm.org/D31396