[llvm] r300665 - [ARM] GlobalISel: Add support for G_MUL
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 19 00:29:46 PDT 2017
Author: rovka
Date: Wed Apr 19 02:29:46 2017
New Revision: 300665
URL: http://llvm.org/viewvc/llvm-project?rev=300665&view=rev
Log:
[ARM] GlobalISel: Add support for G_MUL
Support G_MUL, very similar to G_ADD and G_SUB. The only difference is
in the instruction selector, where we have to select either MUL or MULv5
depending on the target.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=300665&r1=300664&r2=300665&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Wed Apr 19 02:29:46 2017
@@ -303,6 +303,16 @@ bool ARMInstructionSelector::select(Mach
I.setDesc(TII.get(ARM::SUBrr));
MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
break;
+ case G_MUL:
+ if (TII.getSubtarget().hasV6Ops()) {
+ I.setDesc(TII.get(ARM::MUL));
+ } else {
+ assert(TII.getSubtarget().useMulOps() && "Unsupported target");
+ I.setDesc(TII.get(ARM::MULv5));
+ MIB->getOperand(0).setIsEarlyClobber(true);
+ }
+ MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
+ break;
case G_FADD:
if (!selectFAdd(MIB, TII, MRI))
return false;
Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=300665&r1=300664&r2=300665&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Wed Apr 19 02:29:46 2017
@@ -43,7 +43,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const
setAction({Op, 1, p0}, Legal);
}
- for (unsigned Op : {G_ADD, G_SUB})
+ for (unsigned Op : {G_ADD, G_SUB, G_MUL})
for (auto Ty : {s1, s8, s16, s32})
setAction({Op, Ty}, Legal);
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=300665&r1=300664&r2=300665&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Wed Apr 19 02:29:46 2017
@@ -220,6 +220,7 @@ ARMRegisterBankInfo::getInstrMapping(con
switch (Opc) {
case G_ADD:
case G_SUB:
+ case G_MUL:
case G_SEXT:
case G_ZEXT:
case G_GEP:
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=300665&r1=300664&r2=300665&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Wed Apr 19 02:29:46 2017
@@ -16,6 +16,11 @@
define void @test_sub_s16() { ret void }
define void @test_sub_s32() { ret void }
+ define void @test_mul_s8() #1 { ret void }
+ define void @test_mul_s16() #1 { ret void }
+ define void @test_mul_s32() #1 { ret void }
+ define void @test_mulv5_s32() { ret void }
+
define void @test_load_from_stack() { ret void }
define void @test_load_f32() #0 { ret void }
define void @test_load_f64() #0 { ret void }
@@ -28,6 +33,7 @@
define void @test_soft_fp_double() #0 { ret void }
attributes #0 = { "target-features"="+vfp2,-neonfp" }
+ attributes #1 = { "target-features"="+v6" }
...
---
name: test_zext_s1
@@ -395,6 +401,138 @@ body: |
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
+
+ BX_RET 14, _, implicit %r0
+ ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name: test_mul_s8
+# CHECK-LABEL: name: test_mul_s8
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+# CHECK-DAG: id: 0, class: gprnopc
+# CHECK-DAG: id: 1, class: gprnopc
+# CHECK-DAG: id: 2, class: gprnopc
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s8) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+
+ %1(s8) = COPY %r1
+ ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+
+ %2(s8) = G_MUL %0, %1
+ ; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGX]], [[VREGY]], 14, _, _
+
+ %r0 = COPY %2(s8)
+ ; CHECK: %r0 = COPY [[VREGRES]]
+
+ BX_RET 14, _, implicit %r0
+ ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name: test_mul_s16
+# CHECK-LABEL: name: test_mul_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+# CHECK-DAG: id: 0, class: gprnopc
+# CHECK-DAG: id: 1, class: gprnopc
+# CHECK-DAG: id: 2, class: gprnopc
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s16) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+
+ %1(s16) = COPY %r1
+ ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+
+ %2(s16) = G_MUL %0, %1
+ ; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGX]], [[VREGY]], 14, _, _
+
+ %r0 = COPY %2(s16)
+ ; CHECK: %r0 = COPY [[VREGRES]]
+
+ BX_RET 14, _, implicit %r0
+ ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name: test_mul_s32
+# CHECK-LABEL: name: test_mul_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+# CHECK: id: 0, class: gprnopc
+# CHECK: id: 1, class: gprnopc
+# CHECK: id: 2, class: gprnopc
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+
+ %1(s32) = COPY %r1
+ ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+
+ %2(s32) = G_MUL %0, %1
+ ; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGX]], [[VREGY]], 14, _, _
+
+ %r0 = COPY %2(s32)
+ ; CHECK: %r0 = COPY [[VREGRES]]
+
+ BX_RET 14, _, implicit %r0
+ ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name: test_mulv5_s32
+# CHECK-LABEL: name: test_mulv5_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+# CHECK: id: 0, class: gprnopc
+# CHECK: id: 1, class: gprnopc
+# CHECK: id: 2, class: gprnopc
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+
+ %1(s32) = COPY %r1
+ ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+
+ %2(s32) = G_MUL %0, %1
+ ; CHECK: early-clobber [[VREGRES:%[0-9]+]] = MULv5 [[VREGX]], [[VREGY]], 14, _, _
+
+ %r0 = COPY %2(s32)
+ ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll?rev=300665&r1=300664&r2=300665&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll Wed Apr 19 02:29:46 2017
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple arm-unknown -mattr=+vfp2 -global-isel %s -o - | FileCheck %s
+; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v6 -global-isel %s -o - | FileCheck %s
define void @test_void_return() {
; CHECK-LABEL: test_void_return:
@@ -94,6 +94,33 @@ entry:
ret i32 %sum
}
+define i8 @test_mul_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: test_mul_i8:
+; CHECK: mul r0, r0, r1
+; CHECK: bx lr
+entry:
+ %sum = mul i8 %x, %y
+ ret i8 %sum
+}
+
+define i16 @test_mul_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: test_mul_i16:
+; CHECK: mul r0, r0, r1
+; CHECK: bx lr
+entry:
+ %sum = mul i16 %x, %y
+ ret i16 %sum
+}
+
+define i32 @test_mul_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: test_mul_i32:
+; CHECK: mul r0, r0, r1
+; CHECK: bx lr
+entry:
+ %sum = mul i32 %x, %y
+ ret i32 %sum
+}
+
define i32 @test_stack_args_i32(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
; CHECK-LABEL: test_stack_args_i32:
; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir?rev=300665&r1=300664&r2=300665&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir Wed Apr 19 02:29:46 2017
@@ -11,6 +11,10 @@
define void @test_sub_s16() { ret void }
define void @test_sub_s32() { ret void }
+ define void @test_mul_s8() { ret void }
+ define void @test_mul_s16() { ret void }
+ define void @test_mul_s32() { ret void }
+
define void @test_load_from_stack() { ret void }
define void @test_legal_loads() #0 { ret void }
define void @test_legal_stores() #0 { ret void }
@@ -215,6 +219,80 @@ body: |
%r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0
+...
+---
+name: test_mul_s8
+# CHECK-LABEL: name: test_mul_s8
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s8) = COPY %r0
+ %1(s8) = COPY %r1
+ %2(s8) = G_MUL %0, %1
+ ; G_MUL with s8 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
+ %r0 = COPY %2(s8)
+ BX_RET 14, _, implicit %r0
+...
+---
+name: test_mul_s16
+# CHECK-LABEL: name: test_mul_s16
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s16) = COPY %r0
+ %1(s16) = COPY %r1
+ %2(s16) = G_MUL %0, %1
+ ; G_MUL with s16 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
+ %r0 = COPY %2(s16)
+ BX_RET 14, _, implicit %r0
+
+...
+---
+name: test_mul_s32
+# CHECK-LABEL: name: test_mul_s32
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ %2(s32) = G_MUL %0, %1
+ ; G_MUL with s32 is legal, so we should find it unchanged in the output
+ ; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
+ %r0 = COPY %2(s32)
+ BX_RET 14, _, implicit %r0
+
...
---
name: test_load_from_stack
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=300665&r1=300664&r2=300665&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Wed Apr 19 02:29:46 2017
@@ -9,6 +9,10 @@
define void @test_sub_s16() { ret void }
define void @test_sub_s8() { ret void }
+ define void @test_mul_s32() { ret void }
+ define void @test_mul_s16() { ret void }
+ define void @test_mul_s8() { ret void }
+
define void @test_loads() #0 { ret void }
define void @test_stores() #0 { ret void }
@@ -206,6 +210,84 @@ body: |
%r0 = COPY %2(s8)
BX_RET 14, _, implicit %r0
+...
+---
+name: test_mul_s32
+# CHECK-LABEL: name: test_mul_s32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 2, class: gprb }
+
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ %2(s32) = G_MUL %0, %1
+ %r0 = COPY %2(s32)
+ BX_RET 14, _, implicit %r0
+
+...
+---
+name: test_mul_s16
+# CHECK-LABEL: name: test_mul_s16
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 2, class: gprb }
+
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s16) = COPY %r0
+ %1(s16) = COPY %r1
+ %2(s16) = G_MUL %0, %1
+ %r0 = COPY %2(s16)
+ BX_RET 14, _, implicit %r0
+
+...
+---
+name: test_mul_s8
+# CHECK-LABEL: name: test_mul_s8
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+# CHECK: - { id: 2, class: gprb }
+
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ %0(s8) = COPY %r0
+ %1(s8) = COPY %r1
+ %2(s8) = G_MUL %0, %1
+ %r0 = COPY %2(s8)
+ BX_RET 14, _, implicit %r0
+
...
---
name: test_loads
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