[PATCH] D31944: [DAGCombiner] add (sext i1 X), 1 --> zext (not i1 X)

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

I'm not sure this is consistently beneficial; particularly for vectors, if the operand is a comparison (or something derived from a comparison), sign-extending it could be free.


https://reviews.llvm.org/D31944