[llvm] r300547 - [ARM] Add hardware build attributes in assembler
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 18 05:52:38 PDT 2017
Author: olista01
Date: Tue Apr 18 07:52:35 2017
New Revision: 300547
URL: http://llvm.org/viewvc/llvm-project?rev=300547&view=rev
Log:
[ARM] Add hardware build attributes in assembler
In the assembler, we should emit build attributes based on the target
selected with command-line options. This matches the GNU assembler's
behaviour. We only do this for build attributes which describe the
hardware that is expected to be available, not the ones that describe
ABI compatibility.
This is done by moving some of the attribute emission code to
ARMTargetStreamer, so that it can be shared between the assembly and
code-generation code paths. Since the assembler only creates a
MCSubtargetInfo, not an ARMSubtarget, the code had to be changed to
check raw features, and not use the convenience functions in
ARMSubtarget.
If different attributes are later specified using the .eabi_attribute
directive, then they will take precedence, as happens when the same
.eabi_attribute is specified twice.
This must be enabled by an option, because we don't want to do this when
parsing inline assembly. The attributes would match the ones emitted at
the start of the file, so wouldn't actually change the emitted object
file, but the extra directives would be added to every inline assembly
block when emitting assembly, which we'd like to avoid.
The majority of the changes in the build-attributes.ll test are just
re-ordering the directives, because the hardware attributes are now
emitted before the ABI ones. However, I did fix one bug which I spotted:
Tag_CPU_arch_profile was not being emitted for v6M.
Differential revision: https://reviews.llvm.org/D31812
Added:
llvm/trunk/test/MC/ARM/assembly-default-build-attributes.s
Modified:
llvm/trunk/include/llvm/MC/MCStreamer.h
llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
llvm/trunk/test/CodeGen/ARM/build-attributes.ll
Modified: llvm/trunk/include/llvm/MC/MCStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=300547&r1=300546&r2=300547&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCStreamer.h (original)
+++ llvm/trunk/include/llvm/MC/MCStreamer.h Tue Apr 18 07:52:35 2017
@@ -128,6 +128,7 @@ public:
virtual void emitArch(unsigned Arch);
virtual void emitArchExtension(unsigned ArchExt);
virtual void emitObjectArch(unsigned Arch);
+ void emitTargetAttributes(const MCSubtargetInfo &STI);
virtual void finishAttributeSection();
virtual void emitInst(uint32_t Inst, char Suffix = '\0');
Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSubtargetInfo.h?rev=300547&r1=300546&r2=300547&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Tue Apr 18 07:52:35 2017
@@ -86,6 +86,10 @@ public:
FeatureBits = FeatureBits_;
}
+ bool hasFeature(unsigned Feature) const {
+ return FeatureBits[Feature];
+ }
+
protected:
/// Initialize the scheduling model and feature bits.
///
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=300547&r1=300546&r2=300547&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Apr 18 07:52:35 2017
@@ -589,12 +589,6 @@ void ARMAsmPrinter::EmitEndOfAsmFile(Mod
ATS.finishAttributeSection();
}
-static bool isV8M(const ARMSubtarget *Subtarget) {
- // Note that v8M Baseline is a subset of v6T2!
- return (Subtarget->hasV8MBaselineOps() && !Subtarget->hasV6T2Ops()) ||
- Subtarget->hasV8MMainlineOps();
-}
-
//===----------------------------------------------------------------------===//
// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
// FIXME:
@@ -602,39 +596,6 @@ static bool isV8M(const ARMSubtarget *Su
// to appear in the .ARM.attributes section in ELF.
// Instead of subclassing the MCELFStreamer, we do the work here.
-static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
- const ARMSubtarget *Subtarget) {
- if (CPU == "xscale")
- return ARMBuildAttrs::v5TEJ;
-
- if (Subtarget->hasV8Ops()) {
- if (Subtarget->isRClass())
- return ARMBuildAttrs::v8_R;
- return ARMBuildAttrs::v8_A;
- } else if (Subtarget->hasV8MMainlineOps())
- return ARMBuildAttrs::v8_M_Main;
- else if (Subtarget->hasV7Ops()) {
- if (Subtarget->isMClass() && Subtarget->hasDSP())
- return ARMBuildAttrs::v7E_M;
- return ARMBuildAttrs::v7;
- } else if (Subtarget->hasV6T2Ops())
- return ARMBuildAttrs::v6T2;
- else if (Subtarget->hasV8MBaselineOps())
- return ARMBuildAttrs::v8_M_Base;
- else if (Subtarget->hasV6MOps())
- return ARMBuildAttrs::v6S_M;
- else if (Subtarget->hasV6Ops())
- return ARMBuildAttrs::v6;
- else if (Subtarget->hasV5TEOps())
- return ARMBuildAttrs::v5TE;
- else if (Subtarget->hasV5TOps())
- return ARMBuildAttrs::v5T;
- else if (Subtarget->hasV4TOps())
- return ARMBuildAttrs::v4T;
- else
- return ARMBuildAttrs::v4;
-}
-
// Returns true if all functions have the same function attribute value.
// It also returns true when the module has no functions.
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
@@ -671,89 +632,8 @@ void ARMAsmPrinter::emitAttributes() {
static_cast<const ARMBaseTargetMachine &>(TM);
const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
- const std::string &CPUString = STI.getCPUString();
-
- if (!StringRef(CPUString).startswith("generic")) {
- // FIXME: remove krait check when GNU tools support krait cpu
- if (STI.isKrait()) {
- ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
- // We consider krait as a "cortex-a9" + hwdiv CPU
- // Enable hwdiv through ".arch_extension idiv"
- if (STI.hasDivide() || STI.hasDivideInARMMode())
- ATS.emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM);
- } else
- ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
- }
-
- ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
-
- // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
- // profile is not applicable (e.g. pre v7, or cross-profile code)".
- if (STI.hasV7Ops() || isV8M(&STI)) {
- if (STI.isAClass()) {
- ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
- ARMBuildAttrs::ApplicationProfile);
- } else if (STI.isRClass()) {
- ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
- ARMBuildAttrs::RealTimeProfile);
- } else if (STI.isMClass()) {
- ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
- ARMBuildAttrs::MicroControllerProfile);
- }
- }
-
- ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
- STI.hasARMOps() ? ARMBuildAttrs::Allowed
- : ARMBuildAttrs::Not_Allowed);
- if (isV8M(&STI)) {
- ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
- ARMBuildAttrs::AllowThumbDerived);
- } else if (STI.isThumb1Only()) {
- ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
- } else if (STI.hasThumb2()) {
- ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
- ARMBuildAttrs::AllowThumb32);
- }
-
- if (STI.hasNEON()) {
- /* NEON is not exactly a VFP architecture, but GAS emit one of
- * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
- if (STI.hasFPARMv8()) {
- if (STI.hasCrypto())
- ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
- else
- ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
- } else if (STI.hasVFP4())
- ATS.emitFPU(ARM::FK_NEON_VFPV4);
- else
- ATS.emitFPU(STI.hasFP16() ? ARM::FK_NEON_FP16 : ARM::FK_NEON);
- // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
- if (STI.hasV8Ops())
- ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
- STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
- ARMBuildAttrs::AllowNeonARMv8);
- } else {
- if (STI.hasFPARMv8())
- // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
- // FPU, but there are two different names for it depending on the CPU.
- ATS.emitFPU(STI.hasD16()
- ? (STI.isFPOnlySP() ? ARM::FK_FPV5_SP_D16 : ARM::FK_FPV5_D16)
- : ARM::FK_FP_ARMV8);
- else if (STI.hasVFP4())
- ATS.emitFPU(STI.hasD16()
- ? (STI.isFPOnlySP() ? ARM::FK_FPV4_SP_D16 : ARM::FK_VFPV4_D16)
- : ARM::FK_VFPV4);
- else if (STI.hasVFP3())
- ATS.emitFPU(STI.hasD16()
- // +d16
- ? (STI.isFPOnlySP()
- ? (STI.hasFP16() ? ARM::FK_VFPV3XD_FP16 : ARM::FK_VFPV3XD)
- : (STI.hasFP16() ? ARM::FK_VFPV3_D16_FP16 : ARM::FK_VFPV3_D16))
- // -d16
- : (STI.hasFP16() ? ARM::FK_VFPV3_FP16 : ARM::FK_VFPV3));
- else if (STI.hasVFP2())
- ATS.emitFPU(ARM::FK_VFPV2);
- }
+ // Emit build attributes for the available hardware.
+ ATS.emitTargetAttributes(STI);
// RW data addressing.
if (isPositionIndependent()) {
@@ -846,32 +726,15 @@ void ARMAsmPrinter::emitAttributes() {
ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
ARMBuildAttrs::AllowIEEE754);
- if (STI.allowsUnalignedMem())
- ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
- ARMBuildAttrs::Allowed);
- else
- ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
- ARMBuildAttrs::Not_Allowed);
-
// FIXME: add more flags to ARMBuildAttributes.h
// 8-bytes alignment stuff.
ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
- // ABI_HardFP_use attribute to indicate single precision FP.
- if (STI.isFPOnlySP())
- ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
- ARMBuildAttrs::HardFPSinglePrecision);
-
// Hard float. Use both S and D registers and conform to AAPCS-VFP.
if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
- // FIXME: Should we signal R9 usage?
-
- if (STI.hasFP16())
- ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
-
// FIXME: To support emitting this build attribute as GCC does, the
// -mfp16-format option and associated plumbing must be
// supported. For now the __fp16 type is exposed by default, so this
@@ -879,21 +742,6 @@ void ARMAsmPrinter::emitAttributes() {
ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
ARMBuildAttrs::FP16FormatIEEE);
- if (STI.hasMPExtension())
- ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
-
- // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
- // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
- // It is not possible to produce DisallowDIV: if hwdiv is present in the base
- // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
- // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
- // otherwise, the default value (AllowDIVIfExists) applies.
- if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
- ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
-
- if (STI.hasDSP() && isV8M(&STI))
- ATS.emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
-
if (MMI) {
if (const Module *SourceModule = MMI->getModule()) {
// ABI_PCS_wchar_t to indicate wchar_t width
@@ -930,16 +778,6 @@ void ARMAsmPrinter::emitAttributes() {
else
ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
ARMBuildAttrs::R9IsGPR);
-
- if (STI.hasTrustZone() && STI.hasVirtualization())
- ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
- ARMBuildAttrs::AllowTZVirtualization);
- else if (STI.hasTrustZone())
- ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
- ARMBuildAttrs::AllowTZ);
- else if (STI.hasVirtualization())
- ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
- ARMBuildAttrs::AllowVirtualization);
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=300547&r1=300546&r2=300547&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Apr 18 07:52:35 2017
@@ -67,6 +67,9 @@ static cl::opt<ImplicitItModeTy> Implici
clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
"Warn in ARM, emit implicit ITs in Thumb")));
+static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
+ cl::init(false));
+
class ARMOperand;
enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
@@ -540,6 +543,10 @@ public:
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
+ // Add build attributes based on the selected target.
+ if (AddBuildAttributes)
+ getTargetStreamer().emitTargetAttributes(STI);
+
// Not in an ITBlock to start with.
ITState.CurPosition = ~0U;
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp?rev=300547&r1=300546&r2=300547&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp Tue Apr 18 07:52:35 2017
@@ -11,9 +11,13 @@
//
//===----------------------------------------------------------------------===//
+#include "ARMTargetMachine.h"
#include "llvm/MC/ConstantPools.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/ARMBuildAttributes.h"
+#include "llvm/Support/TargetParser.h"
using namespace llvm;
@@ -75,3 +79,179 @@ void ARMTargetStreamer::emitInst(uint32_
void
ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {}
void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {}
+
+static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) {
+ if (STI.getCPU() == "xscale")
+ return ARMBuildAttrs::v5TEJ;
+
+ if (STI.hasFeature(ARM::HasV8Ops)) {
+ if (STI.hasFeature(ARM::FeatureRClass))
+ return ARMBuildAttrs::v8_R;
+ return ARMBuildAttrs::v8_A;
+ } else if (STI.hasFeature(ARM::HasV8MMainlineOps))
+ return ARMBuildAttrs::v8_M_Main;
+ else if (STI.hasFeature(ARM::HasV7Ops)) {
+ if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP))
+ return ARMBuildAttrs::v7E_M;
+ return ARMBuildAttrs::v7;
+ } else if (STI.hasFeature(ARM::HasV6T2Ops))
+ return ARMBuildAttrs::v6T2;
+ else if (STI.hasFeature(ARM::HasV8MBaselineOps))
+ return ARMBuildAttrs::v8_M_Base;
+ else if (STI.hasFeature(ARM::HasV6MOps))
+ return ARMBuildAttrs::v6S_M;
+ else if (STI.hasFeature(ARM::HasV6Ops))
+ return ARMBuildAttrs::v6;
+ else if (STI.hasFeature(ARM::HasV5TEOps))
+ return ARMBuildAttrs::v5TE;
+ else if (STI.hasFeature(ARM::HasV5TOps))
+ return ARMBuildAttrs::v5T;
+ else if (STI.hasFeature(ARM::HasV4TOps))
+ return ARMBuildAttrs::v4T;
+ else
+ return ARMBuildAttrs::v4;
+}
+
+static bool isV8M(const MCSubtargetInfo &STI) {
+ // Note that v8M Baseline is a subset of v6T2!
+ return (STI.hasFeature(ARM::HasV8MBaselineOps) &&
+ !STI.hasFeature(ARM::HasV6T2Ops)) ||
+ STI.hasFeature(ARM::HasV8MMainlineOps);
+}
+
+/// Emit the build attributes that only depend on the hardware that we expect
+// /to be available, and not on the ABI, or any source-language choices.
+void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
+ switchVendor("aeabi");
+
+ const StringRef CPUString = STI.getCPU();
+ if (!CPUString.empty() && !CPUString.startswith("generic")) {
+ // FIXME: remove krait check when GNU tools support krait cpu
+ if (STI.hasFeature(ARM::ProcKrait)) {
+ emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
+ // We consider krait as a "cortex-a9" + hwdiv CPU
+ // Enable hwdiv through ".arch_extension idiv"
+ if (STI.hasFeature(ARM::FeatureHWDiv) ||
+ STI.hasFeature(ARM::FeatureHWDivARM))
+ emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM);
+ } else {
+ emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
+ }
+ }
+
+ emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(STI));
+
+ if (STI.hasFeature(ARM::FeatureAClass)) {
+ emitAttribute(ARMBuildAttrs::CPU_arch_profile,
+ ARMBuildAttrs::ApplicationProfile);
+ } else if (STI.hasFeature(ARM::FeatureRClass)) {
+ emitAttribute(ARMBuildAttrs::CPU_arch_profile,
+ ARMBuildAttrs::RealTimeProfile);
+ } else if (STI.hasFeature(ARM::FeatureMClass)) {
+ emitAttribute(ARMBuildAttrs::CPU_arch_profile,
+ ARMBuildAttrs::MicroControllerProfile);
+ }
+
+ emitAttribute(ARMBuildAttrs::ARM_ISA_use, STI.hasFeature(ARM::FeatureNoARM)
+ ? ARMBuildAttrs::Not_Allowed
+ : ARMBuildAttrs::Allowed);
+
+ if (isV8M(STI)) {
+ emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
+ ARMBuildAttrs::AllowThumbDerived);
+ } else if (STI.hasFeature(ARM::FeatureThumb2)) {
+ emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
+ ARMBuildAttrs::AllowThumb32);
+ } else if (STI.hasFeature(ARM::HasV4TOps)) {
+ emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
+ }
+
+ if (STI.hasFeature(ARM::FeatureNEON)) {
+ /* NEON is not exactly a VFP architecture, but GAS emit one of
+ * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
+ if (STI.hasFeature(ARM::FeatureFPARMv8)) {
+ if (STI.hasFeature(ARM::FeatureCrypto))
+ emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
+ else
+ emitFPU(ARM::FK_NEON_FP_ARMV8);
+ } else if (STI.hasFeature(ARM::FeatureVFP4))
+ emitFPU(ARM::FK_NEON_VFPV4);
+ else
+ emitFPU(STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_NEON_FP16
+ : ARM::FK_NEON);
+ // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
+ if (STI.hasFeature(ARM::HasV8Ops))
+ emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
+ STI.hasFeature(ARM::HasV8_1aOps)
+ ? ARMBuildAttrs::AllowNeonARMv8_1a
+ : ARMBuildAttrs::AllowNeonARMv8);
+ } else {
+ if (STI.hasFeature(ARM::FeatureFPARMv8))
+ // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
+ // FPU, but there are two different names for it depending on the CPU.
+ emitFPU(STI.hasFeature(ARM::FeatureD16)
+ ? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV5_SP_D16
+ : ARM::FK_FPV5_D16)
+ : ARM::FK_FP_ARMV8);
+ else if (STI.hasFeature(ARM::FeatureVFP4))
+ emitFPU(STI.hasFeature(ARM::FeatureD16)
+ ? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV4_SP_D16
+ : ARM::FK_VFPV4_D16)
+ : ARM::FK_VFPV4);
+ else if (STI.hasFeature(ARM::FeatureVFP3))
+ emitFPU(
+ STI.hasFeature(ARM::FeatureD16)
+ // +d16
+ ? (STI.hasFeature(ARM::FeatureVFPOnlySP)
+ ? (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16
+ : ARM::FK_VFPV3XD)
+ : (STI.hasFeature(ARM::FeatureFP16)
+ ? ARM::FK_VFPV3_D16_FP16
+ : ARM::FK_VFPV3_D16))
+ // -d16
+ : (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16
+ : ARM::FK_VFPV3));
+ else if (STI.hasFeature(ARM::FeatureVFP2))
+ emitFPU(ARM::FK_VFPV2);
+ }
+
+ // ABI_HardFP_use attribute to indicate single precision FP.
+ if (STI.hasFeature(ARM::FeatureVFPOnlySP))
+ emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
+ ARMBuildAttrs::HardFPSinglePrecision);
+
+ if (STI.hasFeature(ARM::FeatureFP16))
+ emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
+
+ if (STI.hasFeature(ARM::FeatureMP))
+ emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
+
+ // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
+ // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
+ // It is not possible to produce DisallowDIV: if hwdiv is present in the base
+ // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
+ // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
+ // otherwise, the default value (AllowDIVIfExists) applies.
+ if (STI.hasFeature(ARM::FeatureHWDivARM) && !STI.hasFeature(ARM::HasV8Ops))
+ emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
+
+ if (STI.hasFeature(ARM::FeatureDSP) && isV8M(STI))
+ emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
+
+ if (STI.hasFeature(ARM::FeatureStrictAlign))
+ emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
+ ARMBuildAttrs::Not_Allowed);
+ else
+ emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
+ ARMBuildAttrs::Allowed);
+
+ if (STI.hasFeature(ARM::FeatureTrustZone) &&
+ STI.hasFeature(ARM::FeatureVirtualization))
+ emitAttribute(ARMBuildAttrs::Virtualization_use,
+ ARMBuildAttrs::AllowTZVirtualization);
+ else if (STI.hasFeature(ARM::FeatureTrustZone))
+ emitAttribute(ARMBuildAttrs::Virtualization_use, ARMBuildAttrs::AllowTZ);
+ else if (STI.hasFeature(ARM::FeatureVirtualization))
+ emitAttribute(ARMBuildAttrs::Virtualization_use,
+ ARMBuildAttrs::AllowVirtualization);
+}
Modified: llvm/trunk/test/CodeGen/ARM/build-attributes.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes.ll?rev=300547&r1=300546&r2=300547&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/build-attributes.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/build-attributes.ll Tue Apr 18 07:52:35 2017
@@ -231,6 +231,11 @@
; V6: .eabi_attribute 6, 6
; V6: .eabi_attribute 8, 1
;; We assume round-to-nearest by default (matches GCC)
+; V6-NOT: .eabi_attribute 27
+; V6-NOT: .eabi_attribute 36
+; V6-NOT: .eabi_attribute 42
+; V6-NOT: .eabi_attribute 44
+; V6-NOT: .eabi_attribute 68
; V6-NOT: .eabi_attribute 19
;; The default choice made by llc is for a V6 CPU without an FPU.
;; This is not an interesting detail, but for such CPUs, the default intention is to use
@@ -242,13 +247,8 @@
; V6: .eabi_attribute 23, 3
; V6: .eabi_attribute 24, 1
; V6: .eabi_attribute 25, 1
-; V6-NOT: .eabi_attribute 27
; V6-NOT: .eabi_attribute 28
-; V6-NOT: .eabi_attribute 36
; V6: .eabi_attribute 38, 1
-; V6-NOT: .eabi_attribute 42
-; V6-NOT: .eabi_attribute 44
-; V6-NOT: .eabi_attribute 68
; V6-FAST-NOT: .eabi_attribute 19
;; Despite the V6 CPU having no FPU by default, we chose to flush to
@@ -262,9 +262,14 @@
;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for
;; V6-M, however we don't model the OS extension so this is fine.
; V6M: .eabi_attribute 6, 12
-; V6M-NOT: .eabi_attribute 7
+; V6M: .eabi_attribute 7, 77
; V6M: .eabi_attribute 8, 0
; V6M: .eabi_attribute 9, 1
+; V6M-NOT: .eabi_attribute 27
+; V6M-NOT: .eabi_attribute 36
+; V6M-NOT: .eabi_attribute 42
+; V6M-NOT: .eabi_attribute 44
+; V6M-NOT: .eabi_attribute 68
; V6M-NOT: .eabi_attribute 19
;; The default choice made by llc is for a V6M CPU without an FPU.
;; This is not an interesting detail, but for such CPUs, the default intention is to use
@@ -276,13 +281,8 @@
; V6M: .eabi_attribute 23, 3
; V6M: .eabi_attribute 24, 1
; V6M: .eabi_attribute 25, 1
-; V6M-NOT: .eabi_attribute 27
; V6M-NOT: .eabi_attribute 28
-; V6M-NOT: .eabi_attribute 36
; V6M: .eabi_attribute 38, 1
-; V6M-NOT: .eabi_attribute 42
-; V6M-NOT: .eabi_attribute 44
-; V6M-NOT: .eabi_attribute 68
; V6M-FAST-NOT: .eabi_attribute 19
;; Despite the V6M CPU having no FPU by default, we chose to flush to
@@ -298,6 +298,11 @@
; ARM1156T2F-S: .eabi_attribute 8, 1
; ARM1156T2F-S: .eabi_attribute 9, 2
; ARM1156T2F-S: .fpu vfpv2
+; ARM1156T2F-S-NOT: .eabi_attribute 27
+; ARM1156T2F-S-NOT: .eabi_attribute 36
+; ARM1156T2F-S-NOT: .eabi_attribute 42
+; ARM1156T2F-S-NOT: .eabi_attribute 44
+; ARM1156T2F-S-NOT: .eabi_attribute 68
; ARM1156T2F-S-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; ARM1156T2F-S: .eabi_attribute 20, 1
@@ -306,13 +311,8 @@
; ARM1156T2F-S: .eabi_attribute 23, 3
; ARM1156T2F-S: .eabi_attribute 24, 1
; ARM1156T2F-S: .eabi_attribute 25, 1
-; ARM1156T2F-S-NOT: .eabi_attribute 27
; ARM1156T2F-S-NOT: .eabi_attribute 28
-; ARM1156T2F-S-NOT: .eabi_attribute 36
; ARM1156T2F-S: .eabi_attribute 38, 1
-; ARM1156T2F-S-NOT: .eabi_attribute 42
-; ARM1156T2F-S-NOT: .eabi_attribute 44
-; ARM1156T2F-S-NOT: .eabi_attribute 68
; ARM1156T2F-S-FAST-NOT: .eabi_attribute 19
;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally
@@ -327,6 +327,11 @@
; V7M: .eabi_attribute 7, 77
; V7M: .eabi_attribute 8, 0
; V7M: .eabi_attribute 9, 2
+; V7M-NOT: .eabi_attribute 27
+; V7M-NOT: .eabi_attribute 36
+; V7M-NOT: .eabi_attribute 42
+; V7M-NOT: .eabi_attribute 44
+; V7M-NOT: .eabi_attribute 68
; V7M-NOT: .eabi_attribute 19
;; The default choice made by llc is for a V7M CPU without an FPU.
;; This is not an interesting detail, but for such CPUs, the default intention is to use
@@ -338,13 +343,8 @@
; V7M: .eabi_attribute 23, 3
; V7M: .eabi_attribute 24, 1
; V7M: .eabi_attribute 25, 1
-; V7M-NOT: .eabi_attribute 27
; V7M-NOT: .eabi_attribute 28
-; V7M-NOT: .eabi_attribute 36
; V7M: .eabi_attribute 38, 1
-; V7M-NOT: .eabi_attribute 42
-; V7M-NOT: .eabi_attribute 44
-; V7M-NOT: .eabi_attribute 68
; V7M-FAST-NOT: .eabi_attribute 19
;; Despite the V7M CPU having no FPU by default, we chose to flush
@@ -357,6 +357,11 @@
; V7: .syntax unified
; V7: .eabi_attribute 6, 10
+; V7-NOT: .eabi_attribute 27
+; V7-NOT: .eabi_attribute 36
+; V7-NOT: .eabi_attribute 42
+; V7-NOT: .eabi_attribute 44
+; V7-NOT: .eabi_attribute 68
; V7-NOT: .eabi_attribute 19
;; In safe-maths mode we default to an IEEE 754 compliant choice.
; V7: .eabi_attribute 20, 1
@@ -365,13 +370,8 @@
; V7: .eabi_attribute 23, 3
; V7: .eabi_attribute 24, 1
; V7: .eabi_attribute 25, 1
-; V7-NOT: .eabi_attribute 27
; V7-NOT: .eabi_attribute 28
-; V7-NOT: .eabi_attribute 36
; V7: .eabi_attribute 38, 1
-; V7-NOT: .eabi_attribute 42
-; V7-NOT: .eabi_attribute 44
-; V7-NOT: .eabi_attribute 68
; V7-FAST-NOT: .eabi_attribute 19
;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
@@ -386,6 +386,9 @@
; V7VE: .eabi_attribute 7, 65 @ Tag_CPU_arch_profile
; V7VE: .eabi_attribute 8, 1 @ Tag_ARM_ISA_use
; V7VE: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use
+; V7VE: .eabi_attribute 42, 1 @ Tag_MPextension_use
+; V7VE: .eabi_attribute 44, 2 @ Tag_DIV_use
+; V7VE: .eabi_attribute 68, 3 @ Tag_Virtualization_use
; V7VE: .eabi_attribute 17, 1 @ Tag_ABI_PCS_GOT_use
; V7VE: .eabi_attribute 20, 1 @ Tag_ABI_FP_denormal
; V7VE: .eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions
@@ -393,19 +396,16 @@
; V7VE: .eabi_attribute 24, 1 @ Tag_ABI_align_needed
; V7VE: .eabi_attribute 25, 1 @ Tag_ABI_align_preserved
; V7VE: .eabi_attribute 38, 1 @ Tag_ABI_FP_16bit_format
-; V7VE: .eabi_attribute 42, 1 @ Tag_MPextension_use
-; V7VE: .eabi_attribute 44, 2 @ Tag_DIV_use
-; V7VE: .eabi_attribute 68, 3 @ Tag_Virtualization_use
; V8: .syntax unified
; V8: .eabi_attribute 67, "2.09"
; V8: .eabi_attribute 6, 14
+; V8-NOT: .eabi_attribute 44
; V8-NOT: .eabi_attribute 19
; V8: .eabi_attribute 20, 1
; V8: .eabi_attribute 21, 1
; V8-NOT: .eabi_attribute 22
; V8: .eabi_attribute 23, 3
-; V8-NOT: .eabi_attribute 44
; V8-FAST-NOT: .eabi_attribute 19
;; The default does have an FPU, and for V8-A, it flushes preserving sign.
@@ -496,6 +496,30 @@
; CORTEX-A7-FPUV4: .fpu vfpv4
; CORTEX-A7-CHECK-NOT: .eabi_attribute 19
+
+; Tag_FP_HP_extension
+; CORTEX-A7-CHECK: .eabi_attribute 36, 1
+; CORTEX-A7-NOFPU-NOT: .eabi_attribute 36
+; CORTEX-A7-FPUV4: .eabi_attribute 36, 1
+
+; Tag_MPextension_use
+; CORTEX-A7-CHECK: .eabi_attribute 42, 1
+; CORTEX-A7-NOFPU: .eabi_attribute 42, 1
+; CORTEX-A7-FPUV4: .eabi_attribute 42, 1
+
+; Tag_DIV_use
+; CORTEX-A7-CHECK: .eabi_attribute 44, 2
+; CORTEX-A7-NOFPU: .eabi_attribute 44, 2
+; CORTEX-A7-FPUV4: .eabi_attribute 44, 2
+
+; Tag_DSP_extension
+; CORTEX-A7-CHECK-NOT: .eabi_attribute 46
+
+; Tag_Virtualization_use
+; CORTEX-A7-CHECK: .eabi_attribute 68, 3
+; CORTEX-A7-NOFPU: .eabi_attribute 68, 3
+; CORTEX-A7-FPUV4: .eabi_attribute 68, 3
+
; Tag_ABI_FP_denormal
;; We default to IEEE 754 compliance
; CORTEX-A7-CHECK: .eabi_attribute 20, 1
@@ -535,40 +559,20 @@
; CORTEX-A7-NOFPU: .eabi_attribute 25, 1
; CORTEX-A7-FPUV4: .eabi_attribute 25, 1
-; Tag_FP_HP_extension
-; CORTEX-A7-CHECK: .eabi_attribute 36, 1
-; CORTEX-A7-NOFPU-NOT: .eabi_attribute 36
-; CORTEX-A7-FPUV4: .eabi_attribute 36, 1
-
; Tag_FP_16bit_format
; CORTEX-A7-CHECK: .eabi_attribute 38, 1
; CORTEX-A7-NOFPU: .eabi_attribute 38, 1
; CORTEX-A7-FPUV4: .eabi_attribute 38, 1
-; Tag_MPextension_use
-; CORTEX-A7-CHECK: .eabi_attribute 42, 1
-; CORTEX-A7-NOFPU: .eabi_attribute 42, 1
-; CORTEX-A7-FPUV4: .eabi_attribute 42, 1
-
-; Tag_DIV_use
-; CORTEX-A7-CHECK: .eabi_attribute 44, 2
-; CORTEX-A7-NOFPU: .eabi_attribute 44, 2
-; CORTEX-A7-FPUV4: .eabi_attribute 44, 2
-
-; Tag_DSP_extension
-; CORTEX-A7-CHECK-NOT: .eabi_attribute 46
-
-; Tag_Virtualization_use
-; CORTEX-A7-CHECK: .eabi_attribute 68, 3
-; CORTEX-A7-NOFPU: .eabi_attribute 68, 3
-; CORTEX-A7-FPUV4: .eabi_attribute 68, 3
-
; CORTEX-A5-DEFAULT: .cpu cortex-a5
; CORTEX-A5-DEFAULT: .eabi_attribute 6, 10
; CORTEX-A5-DEFAULT: .eabi_attribute 7, 65
; CORTEX-A5-DEFAULT: .eabi_attribute 8, 1
; CORTEX-A5-DEFAULT: .eabi_attribute 9, 2
; CORTEX-A5-DEFAULT: .fpu neon-vfpv4
+; CORTEX-A5-DEFAULT: .eabi_attribute 42, 1
+; CORTEX-A5-DEFAULT-NOT: .eabi_attribute 44
+; CORTEX-A5-DEFAULT: .eabi_attribute 68, 1
; CORTEX-A5-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A5-DEFAULT: .eabi_attribute 20, 1
@@ -577,9 +581,6 @@
; CORTEX-A5-DEFAULT: .eabi_attribute 23, 3
; CORTEX-A5-DEFAULT: .eabi_attribute 24, 1
; CORTEX-A5-DEFAULT: .eabi_attribute 25, 1
-; CORTEX-A5-DEFAULT: .eabi_attribute 42, 1
-; CORTEX-A5-DEFAULT-NOT: .eabi_attribute 44
-; CORTEX-A5-DEFAULT: .eabi_attribute 68, 1
; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 19
;; The A5 defaults to a VFPv4 FPU, so it flushed preserving the sign when -ffast-math
@@ -595,6 +596,8 @@
; CORTEX-A5-NONEON: .eabi_attribute 8, 1
; CORTEX-A5-NONEON: .eabi_attribute 9, 2
; CORTEX-A5-NONEON: .fpu vfpv4-d16
+; CORTEX-A5-NONEON: .eabi_attribute 42, 1
+; CORTEX-A5-NONEON: .eabi_attribute 68, 1
;; We default to IEEE 754 compliance
; CORTEX-A5-NONEON: .eabi_attribute 20, 1
; CORTEX-A5-NONEON: .eabi_attribute 21, 1
@@ -602,8 +605,6 @@
; CORTEX-A5-NONEON: .eabi_attribute 23, 3
; CORTEX-A5-NONEON: .eabi_attribute 24, 1
; CORTEX-A5-NONEON: .eabi_attribute 25, 1
-; CORTEX-A5-NONEON: .eabi_attribute 42, 1
-; CORTEX-A5-NONEON: .eabi_attribute 68, 1
; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 19
;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
@@ -619,6 +620,8 @@
; CORTEX-A5-NOFPU: .eabi_attribute 8, 1
; CORTEX-A5-NOFPU: .eabi_attribute 9, 2
; CORTEX-A5-NOFPU-NOT: .fpu
+; CORTEX-A5-NOFPU: .eabi_attribute 42, 1
+; CORTEX-A5-NOFPU: .eabi_attribute 68, 1
; CORTEX-A5-NOFPU-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A5-NOFPU: .eabi_attribute 20, 1
@@ -627,8 +630,6 @@
; CORTEX-A5-NOFPU: .eabi_attribute 23, 3
; CORTEX-A5-NOFPU: .eabi_attribute 24, 1
; CORTEX-A5-NOFPU: .eabi_attribute 25, 1
-; CORTEX-A5-NOFPU: .eabi_attribute 42, 1
-; CORTEX-A5-NOFPU: .eabi_attribute 68, 1
; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 19
;; Despite there being no FPU, we chose to flush to zero preserving
@@ -645,6 +646,11 @@
; CORTEX-A8-SOFT: .eabi_attribute 8, 1
; CORTEX-A8-SOFT: .eabi_attribute 9, 2
; CORTEX-A8-SOFT: .fpu neon
+; CORTEX-A8-SOFT-NOT: .eabi_attribute 27
+; CORTEX-A8-SOFT-NOT: .eabi_attribute 36, 1
+; CORTEX-A8-SOFT-NOT: .eabi_attribute 42, 1
+; CORTEX-A8-SOFT-NOT: .eabi_attribute 44
+; CORTEX-A8-SOFT: .eabi_attribute 68, 1
; CORTEX-A8-SOFT-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A8-SOFT: .eabi_attribute 20, 1
@@ -653,13 +659,8 @@
; CORTEX-A8-SOFT: .eabi_attribute 23, 3
; CORTEX-A8-SOFT: .eabi_attribute 24, 1
; CORTEX-A8-SOFT: .eabi_attribute 25, 1
-; CORTEX-A8-SOFT-NOT: .eabi_attribute 27
; CORTEX-A8-SOFT-NOT: .eabi_attribute 28
-; CORTEX-A8-SOFT-NOT: .eabi_attribute 36, 1
; CORTEX-A8-SOFT: .eabi_attribute 38, 1
-; CORTEX-A8-SOFT-NOT: .eabi_attribute 42, 1
-; CORTEX-A8-SOFT-NOT: .eabi_attribute 44
-; CORTEX-A8-SOFT: .eabi_attribute 68, 1
; CORTEX-A9-SOFT: .cpu cortex-a9
; CORTEX-A9-SOFT: .eabi_attribute 6, 10
@@ -667,6 +668,11 @@
; CORTEX-A9-SOFT: .eabi_attribute 8, 1
; CORTEX-A9-SOFT: .eabi_attribute 9, 2
; CORTEX-A9-SOFT: .fpu neon
+; CORTEX-A9-SOFT-NOT: .eabi_attribute 27
+; CORTEX-A9-SOFT: .eabi_attribute 36, 1
+; CORTEX-A9-SOFT: .eabi_attribute 42, 1
+; CORTEX-A9-SOFT-NOT: .eabi_attribute 44
+; CORTEX-A9-SOFT: .eabi_attribute 68, 1
; CORTEX-A9-SOFT-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A9-SOFT: .eabi_attribute 20, 1
@@ -675,13 +681,8 @@
; CORTEX-A9-SOFT: .eabi_attribute 23, 3
; CORTEX-A9-SOFT: .eabi_attribute 24, 1
; CORTEX-A9-SOFT: .eabi_attribute 25, 1
-; CORTEX-A9-SOFT-NOT: .eabi_attribute 27
; CORTEX-A9-SOFT-NOT: .eabi_attribute 28
-; CORTEX-A9-SOFT: .eabi_attribute 36, 1
; CORTEX-A9-SOFT: .eabi_attribute 38, 1
-; CORTEX-A9-SOFT: .eabi_attribute 42, 1
-; CORTEX-A9-SOFT-NOT: .eabi_attribute 44
-; CORTEX-A9-SOFT: .eabi_attribute 68, 1
; CORTEX-A8-SOFT-FAST-NOT: .eabi_attribute 19
; CORTEX-A9-SOFT-FAST-NOT: .eabi_attribute 19
@@ -699,6 +700,10 @@
; CORTEX-A8-HARD: .eabi_attribute 8, 1
; CORTEX-A8-HARD: .eabi_attribute 9, 2
; CORTEX-A8-HARD: .fpu neon
+; CORTEX-A8-HARD-NOT: .eabi_attribute 27
+; CORTEX-A8-HARD-NOT: .eabi_attribute 36, 1
+; CORTEX-A8-HARD-NOT: .eabi_attribute 42, 1
+; CORTEX-A8-HARD: .eabi_attribute 68, 1
; CORTEX-A8-HARD-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A8-HARD: .eabi_attribute 20, 1
@@ -707,12 +712,8 @@
; CORTEX-A8-HARD: .eabi_attribute 23, 3
; CORTEX-A8-HARD: .eabi_attribute 24, 1
; CORTEX-A8-HARD: .eabi_attribute 25, 1
-; CORTEX-A8-HARD-NOT: .eabi_attribute 27
; CORTEX-A8-HARD: .eabi_attribute 28, 1
-; CORTEX-A8-HARD-NOT: .eabi_attribute 36, 1
; CORTEX-A8-HARD: .eabi_attribute 38, 1
-; CORTEX-A8-HARD-NOT: .eabi_attribute 42, 1
-; CORTEX-A8-HARD: .eabi_attribute 68, 1
@@ -722,6 +723,10 @@
; CORTEX-A9-HARD: .eabi_attribute 8, 1
; CORTEX-A9-HARD: .eabi_attribute 9, 2
; CORTEX-A9-HARD: .fpu neon
+; CORTEX-A9-HARD-NOT: .eabi_attribute 27
+; CORTEX-A9-HARD: .eabi_attribute 36, 1
+; CORTEX-A9-HARD: .eabi_attribute 42, 1
+; CORTEX-A9-HARD: .eabi_attribute 68, 1
; CORTEX-A9-HARD-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A9-HARD: .eabi_attribute 20, 1
@@ -730,12 +735,8 @@
; CORTEX-A9-HARD: .eabi_attribute 23, 3
; CORTEX-A9-HARD: .eabi_attribute 24, 1
; CORTEX-A9-HARD: .eabi_attribute 25, 1
-; CORTEX-A9-HARD-NOT: .eabi_attribute 27
; CORTEX-A9-HARD: .eabi_attribute 28, 1
-; CORTEX-A9-HARD: .eabi_attribute 36, 1
; CORTEX-A9-HARD: .eabi_attribute 38, 1
-; CORTEX-A9-HARD: .eabi_attribute 42, 1
-; CORTEX-A9-HARD: .eabi_attribute 68, 1
; CORTEX-A8-HARD-FAST-NOT: .eabi_attribute 19
;; The A8 defaults to a VFPv3 FPU, so it flushes preserving the sign when
@@ -759,6 +760,9 @@
; CORTEX-A12-DEFAULT: .eabi_attribute 8, 1
; CORTEX-A12-DEFAULT: .eabi_attribute 9, 2
; CORTEX-A12-DEFAULT: .fpu neon-vfpv4
+; CORTEX-A12-DEFAULT: .eabi_attribute 42, 1
+; CORTEX-A12-DEFAULT: .eabi_attribute 44, 2
+; CORTEX-A12-DEFAULT: .eabi_attribute 68, 3
; CORTEX-A12-DEFAULT-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A12-DEFAULT: .eabi_attribute 20, 1
@@ -767,9 +771,6 @@
; CORTEX-A12-DEFAULT: .eabi_attribute 23, 3
; CORTEX-A12-DEFAULT: .eabi_attribute 24, 1
; CORTEX-A12-DEFAULT: .eabi_attribute 25, 1
-; CORTEX-A12-DEFAULT: .eabi_attribute 42, 1
-; CORTEX-A12-DEFAULT: .eabi_attribute 44, 2
-; CORTEX-A12-DEFAULT: .eabi_attribute 68, 3
; CORTEX-A12-DEFAULT-FAST-NOT: .eabi_attribute 19
;; The A12 defaults to a VFPv3 FPU, so it flushes preserving the sign when
@@ -785,6 +786,9 @@
; CORTEX-A12-NOFPU: .eabi_attribute 8, 1
; CORTEX-A12-NOFPU: .eabi_attribute 9, 2
; CORTEX-A12-NOFPU-NOT: .fpu
+; CORTEX-A12-NOFPU: .eabi_attribute 42, 1
+; CORTEX-A12-NOFPU: .eabi_attribute 44, 2
+; CORTEX-A12-NOFPU: .eabi_attribute 68, 3
; CORTEX-A12-NOFPU-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A12-NOFPU: .eabi_attribute 20, 1
@@ -793,9 +797,6 @@
; CORTEX-A12-NOFPU: .eabi_attribute 23, 3
; CORTEX-A12-NOFPU: .eabi_attribute 24, 1
; CORTEX-A12-NOFPU: .eabi_attribute 25, 1
-; CORTEX-A12-NOFPU: .eabi_attribute 42, 1
-; CORTEX-A12-NOFPU: .eabi_attribute 44, 2
-; CORTEX-A12-NOFPU: .eabi_attribute 68, 3
; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 19
;; Despite there being no FPU, we chose to flush to zero preserving
@@ -812,6 +813,11 @@
; CORTEX-A15: .eabi_attribute 8, 1
; CORTEX-A15: .eabi_attribute 9, 2
; CORTEX-A15: .fpu neon-vfpv4
+; CORTEX-A15-NOT: .eabi_attribute 27
+; CORTEX-A15: .eabi_attribute 36, 1
+; CORTEX-A15: .eabi_attribute 42, 1
+; CORTEX-A15: .eabi_attribute 44, 2
+; CORTEX-A15: .eabi_attribute 68, 3
; CORTEX-A15-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A15: .eabi_attribute 20, 1
@@ -820,13 +826,8 @@
; CORTEX-A15: .eabi_attribute 23, 3
; CORTEX-A15: .eabi_attribute 24, 1
; CORTEX-A15: .eabi_attribute 25, 1
-; CORTEX-A15-NOT: .eabi_attribute 27
; CORTEX-A15-NOT: .eabi_attribute 28
-; CORTEX-A15: .eabi_attribute 36, 1
; CORTEX-A15: .eabi_attribute 38, 1
-; CORTEX-A15: .eabi_attribute 42, 1
-; CORTEX-A15: .eabi_attribute 44, 2
-; CORTEX-A15: .eabi_attribute 68, 3
; CORTEX-A15-FAST-NOT: .eabi_attribute 19
;; The A15 defaults to a VFPv3 FPU, so it flushes preserving the sign when
@@ -842,6 +843,9 @@
; CORTEX-A17-DEFAULT: .eabi_attribute 8, 1
; CORTEX-A17-DEFAULT: .eabi_attribute 9, 2
; CORTEX-A17-DEFAULT: .fpu neon-vfpv4
+; CORTEX-A17-DEFAULT: .eabi_attribute 42, 1
+; CORTEX-A17-DEFAULT: .eabi_attribute 44, 2
+; CORTEX-A17-DEFAULT: .eabi_attribute 68, 3
; CORTEX-A17-DEFAULT-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A17-DEFAULT: .eabi_attribute 20, 1
@@ -850,9 +854,6 @@
; CORTEX-A17-DEFAULT: .eabi_attribute 23, 3
; CORTEX-A17-DEFAULT: .eabi_attribute 24, 1
; CORTEX-A17-DEFAULT: .eabi_attribute 25, 1
-; CORTEX-A17-DEFAULT: .eabi_attribute 42, 1
-; CORTEX-A17-DEFAULT: .eabi_attribute 44, 2
-; CORTEX-A17-DEFAULT: .eabi_attribute 68, 3
; CORTEX-A17-FAST-NOT: .eabi_attribute 19
;; The A17 defaults to a VFPv3 FPU, so it flushes preserving the sign when
@@ -868,6 +869,9 @@
; CORTEX-A17-NOFPU: .eabi_attribute 8, 1
; CORTEX-A17-NOFPU: .eabi_attribute 9, 2
; CORTEX-A17-NOFPU-NOT: .fpu
+; CORTEX-A17-NOFPU: .eabi_attribute 42, 1
+; CORTEX-A17-NOFPU: .eabi_attribute 44, 2
+; CORTEX-A17-NOFPU: .eabi_attribute 68, 3
; CORTEX-A17-NOFPU-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A17-NOFPU: .eabi_attribute 20, 1
@@ -876,9 +880,6 @@
; CORTEX-A17-NOFPU: .eabi_attribute 23, 3
; CORTEX-A17-NOFPU: .eabi_attribute 24, 1
; CORTEX-A17-NOFPU: .eabi_attribute 25, 1
-; CORTEX-A17-NOFPU: .eabi_attribute 42, 1
-; CORTEX-A17-NOFPU: .eabi_attribute 44, 2
-; CORTEX-A17-NOFPU: .eabi_attribute 68, 3
; CORTEX-A17-NOFPU-NOT: .eabi_attribute 19
;; Despite there being no FPU, we chose to flush to zero preserving
@@ -897,25 +898,25 @@
; CORTEX-M0: .cpu cortex-m0
; CORTEX-M0: .eabi_attribute 6, 12
-; CORTEX-M0-NOT: .eabi_attribute 7
+; CORTEX-M0: .eabi_attribute 7, 77
; CORTEX-M0: .eabi_attribute 8, 0
; CORTEX-M0: .eabi_attribute 9, 1
+; CORTEX-M0-NOT: .eabi_attribute 27
+; CORTEX-M0-NOT: .eabi_attribute 36
+; CORTEX-M0: .eabi_attribute 34, 0
+; CORTEX-M0-NOT: .eabi_attribute 42
+; CORTEX-M0-NOT: .eabi_attribute 44
+; CORTEX-M0-NOT: .eabi_attribute 68
; CORTEX-M0-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-M0: .eabi_attribute 20, 1
; CORTEX-M0: .eabi_attribute 21, 1
; CORTEX-M0-NOT: .eabi_attribute 22
; CORTEX-M0: .eabi_attribute 23, 3
-; CORTEX-M0: .eabi_attribute 34, 0
; CORTEX-M0: .eabi_attribute 24, 1
; CORTEX-M0: .eabi_attribute 25, 1
-; CORTEX-M0-NOT: .eabi_attribute 27
; CORTEX-M0-NOT: .eabi_attribute 28
-; CORTEX-M0-NOT: .eabi_attribute 36
; CORTEX-M0: .eabi_attribute 38, 1
-; CORTEX-M0-NOT: .eabi_attribute 42
-; CORTEX-M0-NOT: .eabi_attribute 44
-; CORTEX-M0-NOT: .eabi_attribute 68
; CORTEX-M0-FAST-NOT: .eabi_attribute 19
;; Despite the M0 CPU having no FPU in this scenario, we chose to
@@ -930,9 +931,14 @@
; CORTEX-M0PLUS: .cpu cortex-m0plus
; CORTEX-M0PLUS: .eabi_attribute 6, 12
-; CORTEX-M0PLUS-NOT: .eabi_attribute 7
+; CORTEX-M0PLUS: .eabi_attribute 7, 77
; CORTEX-M0PLUS: .eabi_attribute 8, 0
; CORTEX-M0PLUS: .eabi_attribute 9, 1
+; CORTEX-M0PLUS-NOT: .eabi_attribute 27
+; CORTEX-M0PLUS-NOT: .eabi_attribute 36
+; CORTEX-M0PLUS-NOT: .eabi_attribute 42
+; CORTEX-M0PLUS-NOT: .eabi_attribute 44
+; CORTEX-M0PLUS-NOT: .eabi_attribute 68
; CORTEX-M0PLUS-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-M0PLUS: .eabi_attribute 20, 1
@@ -941,13 +947,8 @@
; CORTEX-M0PLUS: .eabi_attribute 23, 3
; CORTEX-M0PLUS: .eabi_attribute 24, 1
; CORTEX-M0PLUS: .eabi_attribute 25, 1
-; CORTEX-M0PLUS-NOT: .eabi_attribute 27
; CORTEX-M0PLUS-NOT: .eabi_attribute 28
-; CORTEX-M0PLUS-NOT: .eabi_attribute 36
; CORTEX-M0PLUS: .eabi_attribute 38, 1
-; CORTEX-M0PLUS-NOT: .eabi_attribute 42
-; CORTEX-M0PLUS-NOT: .eabi_attribute 44
-; CORTEX-M0PLUS-NOT: .eabi_attribute 68
; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 19
;; Despite the M0+ CPU having no FPU in this scenario, we chose to
@@ -962,9 +963,14 @@
; CORTEX-M1: .cpu cortex-m1
; CORTEX-M1: .eabi_attribute 6, 12
-; CORTEX-M1-NOT: .eabi_attribute 7
+; CORTEX-M1: .eabi_attribute 7, 77
; CORTEX-M1: .eabi_attribute 8, 0
; CORTEX-M1: .eabi_attribute 9, 1
+; CORTEX-M1-NOT: .eabi_attribute 27
+; CORTEX-M1-NOT: .eabi_attribute 36
+; CORTEX-M1-NOT: .eabi_attribute 42
+; CORTEX-M1-NOT: .eabi_attribute 44
+; CORTEX-M1-NOT: .eabi_attribute 68
; CORTEX-M1-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-M1: .eabi_attribute 20, 1
@@ -973,13 +979,8 @@
; CORTEX-M1: .eabi_attribute 23, 3
; CORTEX-M1: .eabi_attribute 24, 1
; CORTEX-M1: .eabi_attribute 25, 1
-; CORTEX-M1-NOT: .eabi_attribute 27
; CORTEX-M1-NOT: .eabi_attribute 28
-; CORTEX-M1-NOT: .eabi_attribute 36
; CORTEX-M1: .eabi_attribute 38, 1
-; CORTEX-M1-NOT: .eabi_attribute 42
-; CORTEX-M1-NOT: .eabi_attribute 44
-; CORTEX-M1-NOT: .eabi_attribute 68
; CORTEX-M1-FAST-NOT: .eabi_attribute 19
;; Despite the M1 CPU having no FPU in this scenario, we chose to
@@ -994,9 +995,13 @@
; SC000: .cpu sc000
; SC000: .eabi_attribute 6, 12
-; SC000-NOT: .eabi_attribute 7
+; SC000: .eabi_attribute 7, 77
; SC000: .eabi_attribute 8, 0
; SC000: .eabi_attribute 9, 1
+; SC000-NOT: .eabi_attribute 27
+; SC000-NOT: .eabi_attribute 42
+; SC000-NOT: .eabi_attribute 44
+; SC000-NOT: .eabi_attribute 68
; SC000-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; SC000: .eabi_attribute 20, 1
@@ -1005,13 +1010,8 @@
; SC000: .eabi_attribute 23, 3
; SC000: .eabi_attribute 24, 1
; SC000: .eabi_attribute 25, 1
-; SC000-NOT: .eabi_attribute 27
; SC000-NOT: .eabi_attribute 28
-; SC000-NOT: .eabi_attribute 36
; SC000: .eabi_attribute 38, 1
-; SC000-NOT: .eabi_attribute 42
-; SC000-NOT: .eabi_attribute 44
-; SC000-NOT: .eabi_attribute 68
; SC000-FAST-NOT: .eabi_attribute 19
;; Despite the SC000 CPU having no FPU in this scenario, we chose to
@@ -1029,6 +1029,11 @@
; CORTEX-M3: .eabi_attribute 7, 77
; CORTEX-M3: .eabi_attribute 8, 0
; CORTEX-M3: .eabi_attribute 9, 2
+; CORTEX-M3-NOT: .eabi_attribute 27
+; CORTEX-M3-NOT: .eabi_attribute 36
+; CORTEX-M3-NOT: .eabi_attribute 42
+; CORTEX-M3-NOT: .eabi_attribute 44
+; CORTEX-M3-NOT: .eabi_attribute 68
; CORTEX-M3-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-M3: .eabi_attribute 20, 1
@@ -1037,13 +1042,8 @@
; CORTEX-M3: .eabi_attribute 23, 3
; CORTEX-M3: .eabi_attribute 24, 1
; CORTEX-M3: .eabi_attribute 25, 1
-; CORTEX-M3-NOT: .eabi_attribute 27
; CORTEX-M3-NOT: .eabi_attribute 28
-; CORTEX-M3-NOT: .eabi_attribute 36
; CORTEX-M3: .eabi_attribute 38, 1
-; CORTEX-M3-NOT: .eabi_attribute 42
-; CORTEX-M3-NOT: .eabi_attribute 44
-; CORTEX-M3-NOT: .eabi_attribute 68
; CORTEX-M3-FAST-NOT: .eabi_attribute 19
;; Despite there being no FPU, we chose to flush to zero preserving
@@ -1059,6 +1059,11 @@
; SC300: .eabi_attribute 7, 77
; SC300: .eabi_attribute 8, 0
; SC300: .eabi_attribute 9, 2
+; SC300-NOT: .eabi_attribute 27
+; SC300-NOT: .eabi_attribute 36
+; SC300-NOT: .eabi_attribute 42
+; SC300-NOT: .eabi_attribute 44
+; SC300-NOT: .eabi_attribute 68
; SC300-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; SC300: .eabi_attribute 20, 1
@@ -1067,13 +1072,8 @@
; SC300: .eabi_attribute 23, 3
; SC300: .eabi_attribute 24, 1
; SC300: .eabi_attribute 25, 1
-; SC300-NOT: .eabi_attribute 27
; SC300-NOT: .eabi_attribute 28
-; SC300-NOT: .eabi_attribute 36
; SC300: .eabi_attribute 38, 1
-; SC300-NOT: .eabi_attribute 42
-; SC300-NOT: .eabi_attribute 44
-; SC300-NOT: .eabi_attribute 68
; SC300-FAST-NOT: .eabi_attribute 19
;; Despite there being no FPU, we chose to flush to zero preserving
@@ -1090,6 +1090,11 @@
; CORTEX-M4-SOFT: .eabi_attribute 8, 0
; CORTEX-M4-SOFT: .eabi_attribute 9, 2
; CORTEX-M4-SOFT: .fpu fpv4-sp-d16
+; CORTEX-M4-SOFT: .eabi_attribute 27, 1
+; CORTEX-M4-SOFT: .eabi_attribute 36, 1
+; CORTEX-M4-SOFT-NOT: .eabi_attribute 42
+; CORTEX-M4-SOFT-NOT: .eabi_attribute 44
+; CORTEX-M4-SOFT-NOT: .eabi_attribute 68
; CORTEX-M4-SOFT-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-M4-SOFT: .eabi_attribute 20, 1
@@ -1098,13 +1103,8 @@
; CORTEX-M4-SOFT: .eabi_attribute 23, 3
; CORTEX-M4-SOFT: .eabi_attribute 24, 1
; CORTEX-M4-SOFT: .eabi_attribute 25, 1
-; CORTEX-M4-SOFT: .eabi_attribute 27, 1
; CORTEX-M4-SOFT-NOT: .eabi_attribute 28
-; CORTEX-M4-SOFT: .eabi_attribute 36, 1
; CORTEX-M4-SOFT: .eabi_attribute 38, 1
-; CORTEX-M4-SOFT-NOT: .eabi_attribute 42
-; CORTEX-M4-SOFT-NOT: .eabi_attribute 44
-; CORTEX-M4-SOFT-NOT: .eabi_attribute 68
; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 19
;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
@@ -1120,6 +1120,11 @@
; CORTEX-M4-HARD: .eabi_attribute 8, 0
; CORTEX-M4-HARD: .eabi_attribute 9, 2
; CORTEX-M4-HARD: .fpu fpv4-sp-d16
+; CORTEX-M4-HARD: .eabi_attribute 27, 1
+; CORTEX-M4-HARD: .eabi_attribute 36, 1
+; CORTEX-M4-HARD-NOT: .eabi_attribute 42
+; CORTEX-M4-HARD-NOT: .eabi_attribute 44
+; CORTEX-M4-HARD-NOT: .eabi_attribute 68
; CORTEX-M4-HARD-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-M4-HARD: .eabi_attribute 20, 1
@@ -1128,13 +1133,8 @@
; CORTEX-M4-HARD: .eabi_attribute 23, 3
; CORTEX-M4-HARD: .eabi_attribute 24, 1
; CORTEX-M4-HARD: .eabi_attribute 25, 1
-; CORTEX-M4-HARD: .eabi_attribute 27, 1
; CORTEX-M4-HARD: .eabi_attribute 28, 1
-; CORTEX-M4-HARD: .eabi_attribute 36, 1
; CORTEX-M4-HARD: .eabi_attribute 38, 1
-; CORTEX-M4-HARD-NOT: .eabi_attribute 42
-; CORTEX-M4-HARD-NOT: .eabi_attribute 44
-; CORTEX-M4-HARD-NOT: .eabi_attribute 68
; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 19
;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
@@ -1152,6 +1152,11 @@
; CORTEX-M7-SOFT-NOT: .fpu
; CORTEX-M7-SINGLE: .fpu fpv5-sp-d16
; CORTEX-M7-DOUBLE: .fpu fpv5-d16
+; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
+; CORTEX-M7-SINGLE: .eabi_attribute 27, 1
+; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
+; CORTEX-M7: .eabi_attribute 36, 1
+; CORTEX-M7-NOT: .eabi_attribute 44
; CORTEX-M7: .eabi_attribute 17, 1
; CORTEX-M7-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
@@ -1161,12 +1166,7 @@
; CORTEX-M7: .eabi_attribute 23, 3
; CORTEX-M7: .eabi_attribute 24, 1
; CORTEX-M7: .eabi_attribute 25, 1
-; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
-; CORTEX-M7-SINGLE: .eabi_attribute 27, 1
-; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
-; CORTEX-M7: .eabi_attribute 36, 1
; CORTEX-M7: .eabi_attribute 38, 1
-; CORTEX-M7-NOT: .eabi_attribute 44
; CORTEX-M7: .eabi_attribute 14, 0
; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 19
@@ -1186,6 +1186,10 @@
; CORTEX-R4: .eabi_attribute 8, 1
; CORTEX-R4: .eabi_attribute 9, 2
; CORTEX-R4-NOT: .fpu vfpv3-d16
+; CORTEX-R4-NOT: .eabi_attribute 36
+; CORTEX-R4-NOT: .eabi_attribute 42
+; CORTEX-R4-NOT: .eabi_attribute 44
+; CORTEX-R4-NOT: .eabi_attribute 68
; CORTEX-R4-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-R4: .eabi_attribute 20, 1
@@ -1195,11 +1199,7 @@
; CORTEX-R4: .eabi_attribute 24, 1
; CORTEX-R4: .eabi_attribute 25, 1
; CORTEX-R4-NOT: .eabi_attribute 28
-; CORTEX-R4-NOT: .eabi_attribute 36
; CORTEX-R4: .eabi_attribute 38, 1
-; CORTEX-R4-NOT: .eabi_attribute 42
-; CORTEX-R4-NOT: .eabi_attribute 44
-; CORTEX-R4-NOT: .eabi_attribute 68
; CORTEX-R4F: .cpu cortex-r4f
; CORTEX-R4F: .eabi_attribute 6, 10
@@ -1207,6 +1207,11 @@
; CORTEX-R4F: .eabi_attribute 8, 1
; CORTEX-R4F: .eabi_attribute 9, 2
; CORTEX-R4F: .fpu vfpv3-d16
+; CORTEX-R4F-NOT: .eabi_attribute 27, 1
+; CORTEX-R4F-NOT: .eabi_attribute 36
+; CORTEX-R4F-NOT: .eabi_attribute 42
+; CORTEX-R4F-NOT: .eabi_attribute 44
+; CORTEX-R4F-NOT: .eabi_attribute 68
; CORTEX-R4F-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-R4F: .eabi_attribute 20, 1
@@ -1215,13 +1220,8 @@
; CORTEX-R4F: .eabi_attribute 23, 3
; CORTEX-R4F: .eabi_attribute 24, 1
; CORTEX-R4F: .eabi_attribute 25, 1
-; CORTEX-R4F-NOT: .eabi_attribute 27, 1
; CORTEX-R4F-NOT: .eabi_attribute 28
-; CORTEX-R4F-NOT: .eabi_attribute 36
; CORTEX-R4F: .eabi_attribute 38, 1
-; CORTEX-R4F-NOT: .eabi_attribute 42
-; CORTEX-R4F-NOT: .eabi_attribute 44
-; CORTEX-R4F-NOT: .eabi_attribute 68
; CORTEX-R5: .cpu cortex-r5
; CORTEX-R5: .eabi_attribute 6, 10
@@ -1229,6 +1229,11 @@
; CORTEX-R5: .eabi_attribute 8, 1
; CORTEX-R5: .eabi_attribute 9, 2
; CORTEX-R5: .fpu vfpv3-d16
+; CORTEX-R5-NOT: .eabi_attribute 27, 1
+; CORTEX-R5-NOT: .eabi_attribute 36
+; CORTEX-R5: .eabi_attribute 44, 2
+; CORTEX-R5-NOT: .eabi_attribute 42
+; CORTEX-R5-NOT: .eabi_attribute 68
; CORTEX-R5-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-R5: .eabi_attribute 20, 1
@@ -1237,13 +1242,8 @@
; CORTEX-R5: .eabi_attribute 23, 3
; CORTEX-R5: .eabi_attribute 24, 1
; CORTEX-R5: .eabi_attribute 25, 1
-; CORTEX-R5-NOT: .eabi_attribute 27, 1
; CORTEX-R5-NOT: .eabi_attribute 28
-; CORTEX-R5-NOT: .eabi_attribute 36
; CORTEX-R5: .eabi_attribute 38, 1
-; CORTEX-R5-NOT: .eabi_attribute 42
-; CORTEX-R5: .eabi_attribute 44, 2
-; CORTEX-R5-NOT: .eabi_attribute 68
; CORTEX-R5-FAST-NOT: .eabi_attribute 19
;; The R5 has the VFPv3 FP unit, which always flushes preserving sign.
@@ -1258,6 +1258,10 @@
; CORTEX-R7: .eabi_attribute 8, 1
; CORTEX-R7: .eabi_attribute 9, 2
; CORTEX-R7: .fpu vfpv3-d16-fp16
+; CORTEX-R7: .eabi_attribute 36, 1
+; CORTEX-R7: .eabi_attribute 42, 1
+; CORTEX-R7: .eabi_attribute 44, 2
+; CORTEX-R7-NOT: .eabi_attribute 68
; CORTEX-R7-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-R7: .eabi_attribute 20, 1
@@ -1267,11 +1271,7 @@
; CORTEX-R7: .eabi_attribute 24, 1
; CORTEX-R7: .eabi_attribute 25, 1
; CORTEX-R7-NOT: .eabi_attribute 28
-; CORTEX-R7: .eabi_attribute 36, 1
; CORTEX-R7: .eabi_attribute 38, 1
-; CORTEX-R7: .eabi_attribute 42, 1
-; CORTEX-R7: .eabi_attribute 44, 2
-; CORTEX-R7-NOT: .eabi_attribute 68
; CORTEX-R7-FAST-NOT: .eabi_attribute 19
;; The R7 has the VFPv3 FP unit, which always flushes preserving sign.
@@ -1286,6 +1286,10 @@
; CORTEX-R8: .eabi_attribute 8, 1
; CORTEX-R8: .eabi_attribute 9, 2
; CORTEX-R8: .fpu vfpv3-d16-fp16
+; CORTEX-R8: .eabi_attribute 36, 1
+; CORTEX-R8: .eabi_attribute 42, 1
+; CORTEX-R8: .eabi_attribute 44, 2
+; CORTEX-R8-NOT: .eabi_attribute 68
; CORTEX-R8-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-R8: .eabi_attribute 20, 1
@@ -1295,11 +1299,7 @@
; CORTEX-R8: .eabi_attribute 24, 1
; CORTEX-R8: .eabi_attribute 25, 1
; CORTEX-R8-NOT: .eabi_attribute 28
-; CORTEX-R8: .eabi_attribute 36, 1
; CORTEX-R8: .eabi_attribute 38, 1
-; CORTEX-R8: .eabi_attribute 42, 1
-; CORTEX-R8: .eabi_attribute 44, 2
-; CORTEX-R8-NOT: .eabi_attribute 68
; CORTEX-R8-FAST-NOT: .eabi_attribute 19
;; The R8 has the VFPv3 FP unit, which always flushes preserving sign.
@@ -1315,6 +1315,11 @@
; CORTEX-A32: .eabi_attribute 9, 2
; CORTEX-A32: .fpu crypto-neon-fp-armv8
; CORTEX-A32: .eabi_attribute 12, 3
+; CORTEX-A32-NOT: .eabi_attribute 27
+; CORTEX-A32: .eabi_attribute 36, 1
+; CORTEX-A32: .eabi_attribute 42, 1
+; CORTEX-A32-NOT: .eabi_attribute 44
+; CORTEX-A32: .eabi_attribute 68, 3
; CORTEX-A32-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A32: .eabi_attribute 20, 1
@@ -1323,13 +1328,8 @@
; CORTEX-A32: .eabi_attribute 23, 3
; CORTEX-A32: .eabi_attribute 24, 1
; CORTEX-A32: .eabi_attribute 25, 1
-; CORTEX-A32-NOT: .eabi_attribute 27
; CORTEX-A32-NOT: .eabi_attribute 28
-; CORTEX-A32: .eabi_attribute 36, 1
; CORTEX-A32: .eabi_attribute 38, 1
-; CORTEX-A32: .eabi_attribute 42, 1
-; CORTEX-A32-NOT: .eabi_attribute 44
-; CORTEX-A32: .eabi_attribute 68, 3
; CORTEX-A32-FAST-NOT: .eabi_attribute 19
;; The A32 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1343,20 +1343,20 @@
; CORTEX-M23: .eabi_attribute 7, 77
; CORTEX-M23: .eabi_attribute 8, 0
; CORTEX-M23: .eabi_attribute 9, 3
+; CORTEX-M23-NOT: .eabi_attribute 27
+; CORTEX-M23: .eabi_attribute 34, 1
+; CORTEX-M23-NOT: .eabi_attribute 44
; CORTEX-M23: .eabi_attribute 17, 1
;; We default to IEEE 754 compliance
; CORTEX-M23-NOT: .eabi_attribute 19
; CORTEX-M23: .eabi_attribute 20, 1
; CORTEX-M23: .eabi_attribute 21, 1
; CORTEX-M23: .eabi_attribute 23, 3
-; CORTEX-M23: .eabi_attribute 34, 1
; CORTEX-M23: .eabi_attribute 24, 1
-; CORTEX-M23-NOT: .eabi_attribute 27
; CORTEX-M23-NOT: .eabi_attribute 28
; CORTEX-M23: .eabi_attribute 25, 1
; CORTEX-M23: .eabi_attribute 38, 1
; CORTEX-M23: .eabi_attribute 14, 0
-; CORTEX-M23-NOT: .eabi_attribute 44
; CORTEX-M33: .cpu cortex-m33
; CORTEX-M33: .eabi_attribute 6, 17
@@ -1364,21 +1364,21 @@
; CORTEX-M33: .eabi_attribute 8, 0
; CORTEX-M33: .eabi_attribute 9, 3
; CORTEX-M33: .fpu fpv5-sp-d16
+; CORTEX-M33: .eabi_attribute 27, 1
+; CORTEX-M33: .eabi_attribute 36, 1
+; CORTEX-M33-NOT: .eabi_attribute 44
+; CORTEX-M33: .eabi_attribute 46, 1
+; CORTEX-M33: .eabi_attribute 34, 1
; CORTEX-M33: .eabi_attribute 17, 1
;; We default to IEEE 754 compliance
; CORTEX-M23-NOT: .eabi_attribute 19
; CORTEX-M33: .eabi_attribute 20, 1
; CORTEX-M33: .eabi_attribute 21, 1
; CORTEX-M33: .eabi_attribute 23, 3
-; CORTEX-M33: .eabi_attribute 34, 1
; CORTEX-M33: .eabi_attribute 24, 1
; CORTEX-M33: .eabi_attribute 25, 1
-; CORTEX-M33: .eabi_attribute 27, 1
; CORTEX-M33-NOT: .eabi_attribute 28
-; CORTEX-M33: .eabi_attribute 36, 1
; CORTEX-M33: .eabi_attribute 38, 1
-; CORTEX-M33: .eabi_attribute 46, 1
-; CORTEX-M33-NOT: .eabi_attribute 44
; CORTEX-M33: .eabi_attribute 14, 0
; CORTEX-M33-FAST-NOT: .eabi_attribute 19
@@ -1394,6 +1394,11 @@
; CORTEX-A35: .eabi_attribute 9, 2
; CORTEX-A35: .fpu crypto-neon-fp-armv8
; CORTEX-A35: .eabi_attribute 12, 3
+; CORTEX-A35-NOT: .eabi_attribute 27
+; CORTEX-A35: .eabi_attribute 36, 1
+; CORTEX-A35: .eabi_attribute 42, 1
+; CORTEX-A35-NOT: .eabi_attribute 44
+; CORTEX-A35: .eabi_attribute 68, 3
; CORTEX-A35-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A35: .eabi_attribute 20, 1
@@ -1402,13 +1407,8 @@
; CORTEX-A35: .eabi_attribute 23, 3
; CORTEX-A35: .eabi_attribute 24, 1
; CORTEX-A35: .eabi_attribute 25, 1
-; CORTEX-A35-NOT: .eabi_attribute 27
; CORTEX-A35-NOT: .eabi_attribute 28
-; CORTEX-A35: .eabi_attribute 36, 1
; CORTEX-A35: .eabi_attribute 38, 1
-; CORTEX-A35: .eabi_attribute 42, 1
-; CORTEX-A35-NOT: .eabi_attribute 44
-; CORTEX-A35: .eabi_attribute 68, 3
; CORTEX-A35-FAST-NOT: .eabi_attribute 19
;; The A35 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1424,6 +1424,11 @@
; CORTEX-A53: .eabi_attribute 9, 2
; CORTEX-A53: .fpu crypto-neon-fp-armv8
; CORTEX-A53: .eabi_attribute 12, 3
+; CORTEX-A53-NOT: .eabi_attribute 27
+; CORTEX-A53: .eabi_attribute 36, 1
+; CORTEX-A53: .eabi_attribute 42, 1
+; CORTEX-A53-NOT: .eabi_attribute 44
+; CORTEX-A53: .eabi_attribute 68, 3
; CORTEX-A53-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A53: .eabi_attribute 20, 1
@@ -1432,13 +1437,8 @@
; CORTEX-A53: .eabi_attribute 23, 3
; CORTEX-A53: .eabi_attribute 24, 1
; CORTEX-A53: .eabi_attribute 25, 1
-; CORTEX-A53-NOT: .eabi_attribute 27
; CORTEX-A53-NOT: .eabi_attribute 28
-; CORTEX-A53: .eabi_attribute 36, 1
; CORTEX-A53: .eabi_attribute 38, 1
-; CORTEX-A53: .eabi_attribute 42, 1
-; CORTEX-A53-NOT: .eabi_attribute 44
-; CORTEX-A53: .eabi_attribute 68, 3
; CORTEX-A53-FAST-NOT: .eabi_attribute 19
;; The A53 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1454,6 +1454,11 @@
; CORTEX-A57: .eabi_attribute 9, 2
; CORTEX-A57: .fpu crypto-neon-fp-armv8
; CORTEX-A57: .eabi_attribute 12, 3
+; CORTEX-A57-NOT: .eabi_attribute 27
+; CORTEX-A57: .eabi_attribute 36, 1
+; CORTEX-A57: .eabi_attribute 42, 1
+; CORTEX-A57-NOT: .eabi_attribute 44
+; CORTEX-A57: .eabi_attribute 68, 3
; CORTEX-A57-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A57: .eabi_attribute 20, 1
@@ -1462,13 +1467,8 @@
; CORTEX-A57: .eabi_attribute 23, 3
; CORTEX-A57: .eabi_attribute 24, 1
; CORTEX-A57: .eabi_attribute 25, 1
-; CORTEX-A57-NOT: .eabi_attribute 27
; CORTEX-A57-NOT: .eabi_attribute 28
-; CORTEX-A57: .eabi_attribute 36, 1
; CORTEX-A57: .eabi_attribute 38, 1
-; CORTEX-A57: .eabi_attribute 42, 1
-; CORTEX-A57-NOT: .eabi_attribute 44
-; CORTEX-A57: .eabi_attribute 68, 3
; CORTEX-A57-FAST-NOT: .eabi_attribute 19
;; The A57 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1484,6 +1484,11 @@
; CORTEX-A72: .eabi_attribute 9, 2
; CORTEX-A72: .fpu crypto-neon-fp-armv8
; CORTEX-A72: .eabi_attribute 12, 3
+; CORTEX-A72-NOT: .eabi_attribute 27
+; CORTEX-A72: .eabi_attribute 36, 1
+; CORTEX-A72: .eabi_attribute 42, 1
+; CORTEX-A72-NOT: .eabi_attribute 44
+; CORTEX-A72: .eabi_attribute 68, 3
; CORTEX-A72-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A72: .eabi_attribute 20, 1
@@ -1492,13 +1497,8 @@
; CORTEX-A72: .eabi_attribute 23, 3
; CORTEX-A72: .eabi_attribute 24, 1
; CORTEX-A72: .eabi_attribute 25, 1
-; CORTEX-A72-NOT: .eabi_attribute 27
; CORTEX-A72-NOT: .eabi_attribute 28
-; CORTEX-A72: .eabi_attribute 36, 1
; CORTEX-A72: .eabi_attribute 38, 1
-; CORTEX-A72: .eabi_attribute 42, 1
-; CORTEX-A72-NOT: .eabi_attribute 44
-; CORTEX-A72: .eabi_attribute 68, 3
; CORTEX-A72-FAST-NOT: .eabi_attribute 19
;; The A72 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1514,6 +1514,11 @@
; CORTEX-A73: .eabi_attribute 9, 2
; CORTEX-A73: .fpu crypto-neon-fp-armv8
; CORTEX-A73: .eabi_attribute 12, 3
+; CORTEX-A73-NOT: .eabi_attribute 27
+; CORTEX-A73: .eabi_attribute 36, 1
+; CORTEX-A73: .eabi_attribute 42, 1
+; CORTEX-A73-NOT: .eabi_attribute 44
+; CORTEX-A73: .eabi_attribute 68, 3
; CORTEX-A73-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; CORTEX-A73: .eabi_attribute 20, 1
@@ -1522,14 +1527,9 @@
; CORTEX-A73: .eabi_attribute 23, 3
; CORTEX-A73: .eabi_attribute 24, 1
; CORTEX-A73: .eabi_attribute 25, 1
-; CORTEX-A73-NOT: .eabi_attribute 27
; CORTEX-A73-NOT: .eabi_attribute 28
-; CORTEX-A73: .eabi_attribute 36, 1
; CORTEX-A73: .eabi_attribute 38, 1
-; CORTEX-A73: .eabi_attribute 42, 1
-; CORTEX-A73-NOT: .eabi_attribute 44
; CORTEX-A73: .eabi_attribute 14, 0
-; CORTEX-A73: .eabi_attribute 68, 3
; EXYNOS-M1: .cpu exynos-m1
; EXYNOS-M1: .eabi_attribute 6, 14
@@ -1538,6 +1538,11 @@
; EXYNOS-M1: .eabi_attribute 9, 2
; EXYNOS-M1: .fpu crypto-neon-fp-armv8
; EXYNOS-M1: .eabi_attribute 12, 3
+; EXYNOS-M1-NOT: .eabi_attribute 27
+; EXYNOS-M1: .eabi_attribute 36, 1
+; EXYNOS-M1: .eabi_attribute 42, 1
+; EXYNOS-M1-NOT: .eabi_attribute 44
+; EXYNOS-M1: .eabi_attribute 68, 3
; EXYNOS-M1-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; EXYNOS-M1: .eabi_attribute 20, 1
@@ -1546,13 +1551,8 @@
; EXYNOS-M1: .eabi_attribute 23, 3
; EXYNOS-M1: .eabi_attribute 24, 1
; EXYNOS-M1: .eabi_attribute 25, 1
-; EXYNOS-M1-NOT: .eabi_attribute 27
; EXYNOS-M1-NOT: .eabi_attribute 28
-; EXYNOS-M1: .eabi_attribute 36, 1
; EXYNOS-M1: .eabi_attribute 38, 1
-; EXYNOS-M1: .eabi_attribute 42, 1
-; EXYNOS-M1-NOT: .eabi_attribute 44
-; EXYNOS-M1: .eabi_attribute 68, 3
; EXYNOS-M1-FAST-NOT: .eabi_attribute 19
;; The exynos-m1 has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1568,6 +1568,11 @@
; EXYNOS-M2: .eabi_attribute 9, 2
; EXYNOS-M2: .fpu crypto-neon-fp-armv8
; EXYNOS-M2: .eabi_attribute 12, 3
+; EXYNOS-M2-NOT: .eabi_attribute 27
+; EXYNOS-M2: .eabi_attribute 36, 1
+; EXYNOS-M2: .eabi_attribute 42, 1
+; EXYNOS-M2-NOT: .eabi_attribute 44
+; EXYNOS-M2: .eabi_attribute 68, 3
; EXYNOS-M2-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; EXYNOS-M2: .eabi_attribute 20, 1
@@ -1576,13 +1581,8 @@
; EXYNOS-M2: .eabi_attribute 23, 3
; EXYNOS-M2: .eabi_attribute 24, 1
; EXYNOS-M2: .eabi_attribute 25, 1
-; EXYNOS-M2-NOT: .eabi_attribute 27
; EXYNOS-M2-NOT: .eabi_attribute 28
-; EXYNOS-M2: .eabi_attribute 36, 1
; EXYNOS-M2: .eabi_attribute 38, 1
-; EXYNOS-M2: .eabi_attribute 42, 1
-; EXYNOS-M2-NOT: .eabi_attribute 44
-; EXYNOS-M2: .eabi_attribute 68, 3
; EXYNOS-M3: .cpu exynos-m3
; EXYNOS-M3: .eabi_attribute 6, 14
@@ -1591,6 +1591,11 @@
; EXYNOS-M3: .eabi_attribute 9, 2
; EXYNOS-M3: .fpu crypto-neon-fp-armv8
; EXYNOS-M3: .eabi_attribute 12, 3
+; EXYNOS-M3-NOT: .eabi_attribute 27
+; EXYNOS-M3: .eabi_attribute 36, 1
+; EXYNOS-M3: .eabi_attribute 42, 1
+; EXYNOS-M3-NOT: .eabi_attribute 44
+; EXYNOS-M3: .eabi_attribute 68, 3
; EXYNOS-M3-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; EXYNOS-M3: .eabi_attribute 20, 1
@@ -1599,13 +1604,8 @@
; EXYNOS-M3: .eabi_attribute 23, 3
; EXYNOS-M3: .eabi_attribute 24, 1
; EXYNOS-M3: .eabi_attribute 25, 1
-; EXYNOS-M3-NOT: .eabi_attribute 27
; EXYNOS-M3-NOT: .eabi_attribute 28
-; EXYNOS-M3: .eabi_attribute 36, 1
; EXYNOS-M3: .eabi_attribute 38, 1
-; EXYNOS-M3: .eabi_attribute 42, 1
-; EXYNOS-M3-NOT: .eabi_attribute 44
-; EXYNOS-M3: .eabi_attribute 68, 3
; GENERIC-FPU-VFPV3-FP16: .fpu vfpv3-fp16
; GENERIC-FPU-VFPV3-D16-FP16: .fpu vfpv3-d16-fp16
@@ -1619,6 +1619,11 @@
; GENERIC-ARMV8_1-A: .eabi_attribute 9, 2
; GENERIC-ARMV8_1-A: .fpu crypto-neon-fp-armv8
; GENERIC-ARMV8_1-A: .eabi_attribute 12, 4
+; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 27
+; GENERIC-ARMV8_1-A: .eabi_attribute 36, 1
+; GENERIC-ARMV8_1-A: .eabi_attribute 42, 1
+; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 44
+; GENERIC-ARMV8_1-A: .eabi_attribute 68, 3
; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; GENERIC-ARMV8_1-A: .eabi_attribute 20, 1
@@ -1627,13 +1632,8 @@
; GENERIC-ARMV8_1-A: .eabi_attribute 23, 3
; GENERIC-ARMV8_1-A: .eabi_attribute 24, 1
; GENERIC-ARMV8_1-A: .eabi_attribute 25, 1
-; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 27
; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 28
-; GENERIC-ARMV8_1-A: .eabi_attribute 36, 1
; GENERIC-ARMV8_1-A: .eabi_attribute 38, 1
-; GENERIC-ARMV8_1-A: .eabi_attribute 42, 1
-; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 44
-; GENERIC-ARMV8_1-A: .eabi_attribute 68, 3
; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 19
;; GENERIC-ARMV8_1-A has the ARMv8 FP unit, which always flushes preserving sign.
@@ -1670,23 +1670,16 @@
; ARMv8R-SP-NOT: .eabi_attribute 12
; ARMv8R-NEON: .fpu neon-fp-armv8
; ARMv8R-NEON: .eabi_attribute 12, 3 @ Tag_Advanced_SIMD_arch
-; ARMv8R: .eabi_attribute 17, 1 @ Tag_ABI_PCS_GOT_use
-; ARMv8R: .eabi_attribute 20, 1 @ Tag_ABI_FP_denormal
-; ARMv8R: .eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions
-; ARMv8R: .eabi_attribute 23, 3 @ Tag_ABI_FP_number_model
-; ARMv8R: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
-; ARMv8R: .eabi_attribute 24, 1 @ Tag_ABI_align_needed
-; ARMv8R: .eabi_attribute 25, 1 @ Tag_ABI_align_preserved
; ARMv8R-NOFPU-NOT: .eabi_attribute 27
; ARMv8R-SP: .eabi_attribute 27, 1 @ Tag_ABI_HardFP_use
; ARMv8R-NEON-NOT: .eabi_attribute 27
; ARMv8R-NOFPU-NOT: .eabi_attribute 36
; ARMv8R-SP: .eabi_attribute 36, 1 @ Tag_FP_HP_extension
; ARMv8R-NEON: .eabi_attribute 36, 1 @ Tag_FP_HP_extension
-; ARMv8R: .eabi_attribute 38, 1 @ Tag_ABI_FP_16bit_format
; ARMv8R: .eabi_attribute 42, 1 @ Tag_MPextension_use
-; ARMv8R: .eabi_attribute 14, 0 @ Tag_ABI_PCS_R9_use
; ARMv8R: .eabi_attribute 68, 2 @ Tag_Virtualization_use
+; ARMv8R: .eabi_attribute 38, 1 @ Tag_ABI_FP_16bit_format
+; ARMv8R: .eabi_attribute 14, 0 @ Tag_ABI_PCS_R9_use
define i32 @f(i64 %z) {
ret i32 0
Added: llvm/trunk/test/MC/ARM/assembly-default-build-attributes.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/assembly-default-build-attributes.s?rev=300547&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/assembly-default-build-attributes.s (added)
+++ llvm/trunk/test/MC/ARM/assembly-default-build-attributes.s Tue Apr 18 07:52:35 2017
@@ -0,0 +1,43 @@
+// RUN: llvm-mc -triple armv7a < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v7A
+// RUN: llvm-mc -triple armv6m < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v6M
+// RUN: llvm-mc -triple armv7m < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v7M
+// RUN: llvm-mc -triple armv7a -mcpu=cortex-a15 < %s -arm-add-build-attributes | FileCheck %s --check-prefix=Cortex-A15
+
+// This isn't intended to be a through check of the build attributes emitted
+// for each target (that's tested elsewhere), but just to check that the
+// hardware attributes are emitted by the assembler based on the selected
+// target when requested.
+
+// v7A-NOT: .cpu
+// v7A: .eabi_attribute 6, 10 @ Tag_CPU_arch
+// v7A: .eabi_attribute 7, 65 @ Tag_CPU_arch_profile
+// v7A: .eabi_attribute 8, 1 @ Tag_ARM_ISA_use
+// v7A: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use
+// v7A: .fpu neon
+// v7A: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
+
+// v6M-NOT: .cpu
+// v6M: .eabi_attribute 6, 12 @ Tag_CPU_arch
+// v6M: .eabi_attribute 7, 77 @ Tag_CPU_arch_profile
+// v6M: .eabi_attribute 8, 0 @ Tag_ARM_ISA_use
+// v6M: .eabi_attribute 9, 1 @ Tag_THUMB_ISA_use
+// v6M: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
+
+// v7M-NOT: .cpu
+// v7M: .eabi_attribute 6, 10 @ Tag_CPU_arch
+// v7M: .eabi_attribute 7, 77 @ Tag_CPU_arch_profile
+// v7M: .eabi_attribute 8, 0 @ Tag_ARM_ISA_use
+// v7M: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use
+// v7M: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
+
+// Cortex-A15: .cpu cortex-a15
+// Cortex-A15: .eabi_attribute 6, 10 @ Tag_CPU_arch
+// Cortex-A15: .eabi_attribute 7, 65 @ Tag_CPU_arch_profile
+// Cortex-A15: .eabi_attribute 8, 1 @ Tag_ARM_ISA_use
+// Cortex-A15: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use
+// Cortex-A15: .fpu neon-vfpv4
+// Cortex-A15: .eabi_attribute 36, 1 @ Tag_FP_HP_extension
+// Cortex-A15: .eabi_attribute 42, 1 @ Tag_MPextension_use
+// Cortex-A15: .eabi_attribute 44, 2 @ Tag_DIV_use
+// Cortex-A15: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
+// Cortex-A15: .eabi_attribute 68, 3 @ Tag_Virtualization_use
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