[PATCH] D32098: [InstCombine] Use less bitwise operations to handle Instruction::SExt in SimplifyDemandedUseBits. Other improvements.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 17 09:57:41 PDT 2017
craig.topper updated this revision to Diff 95446.
craig.topper added a comment.
Use APInt::isSignBitSet instead of isNegative
https://reviews.llvm.org/D32098
Files:
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Index: lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
===================================================================
--- lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -420,40 +420,37 @@
}
case Instruction::SExt: {
// Compute the bits in the result that are not present in the input.
- unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits();
+ unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits();
- APInt InputDemandedBits = DemandedMask &
- APInt::getLowBitsSet(BitWidth, SrcBitWidth);
+ // If the extend bits are not demanded, convert this into a zero extension.
+ if (DemandedMask.getActiveBits() <= SrcBitWidth) {
+ // Convert to ZExt cast.
+ CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
+ return InsertNewInstWith(NewCast, *I);
+ }
- APInt NewBits(APInt::getBitsSetFrom(BitWidth, SrcBitWidth));
- // If any of the sign extended bits are demanded, we know that the sign
- // bit is demanded.
- if ((NewBits & DemandedMask) != 0)
- InputDemandedBits.setBit(SrcBitWidth-1);
+ APInt InputDemandedBits = DemandedMask.trunc(SrcBitWidth);
- InputDemandedBits = InputDemandedBits.trunc(SrcBitWidth);
- KnownZero = KnownZero.trunc(SrcBitWidth);
- KnownOne = KnownOne.trunc(SrcBitWidth);
- if (SimplifyDemandedBits(I, 0, InputDemandedBits, KnownZero, KnownOne,
- Depth + 1))
- return I;
- InputDemandedBits = InputDemandedBits.zext(BitWidth);
- KnownZero = KnownZero.zext(BitWidth);
- KnownOne = KnownOne.zext(BitWidth);
- assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
+ // Sign extended bits are demanded, so the sign bit is demanded.
+ InputDemandedBits.setSignBit();
- // If the sign bit of the input is known set or clear, then we know the
- // top bits of the result.
+ APInt InputKnownZero(SrcBitWidth, 0), InputKnownOne(SrcBitWidth, 0);
+ if (SimplifyDemandedBits(I, 0, InputDemandedBits, InputKnownZero,
+ InputKnownOne, Depth + 1))
+ return I;
- // If the input sign bit is known zero, or if the NewBits are not demanded
- // convert this into a zero extension.
- if (KnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) {
- // Convert to ZExt cast
+ // If the input sign bit is known zero, convert this into a zero extension.
+ if (InputKnownZero.isSignBitSet()) {
+ // Convert to ZExt cast.
CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
return InsertNewInstWith(NewCast, *I);
- } else if (KnownOne[SrcBitWidth-1]) { // Input sign bit known set
- KnownOne |= NewBits;
}
+
+ // If the sign bit of the input is known set or clear, then we know the
+ // top bits of the result.
+ KnownZero = InputKnownZero.sext(BitWidth);
+ KnownOne = InputKnownOne.sext(BitWidth);
+ assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
break;
}
case Instruction::Add:
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