[llvm] r300335 - [Hexagon] Fix a latent problem with interpreting live-in lane masks

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Fri Apr 14 11:21:55 2017
New Revision: 300335

URL: http://llvm.org/viewvc/llvm-project?rev=300335&view=rev
Log:
[Hexagon] Fix a latent problem with interpreting live-in lane masks

A non-zero lane mask on a register with no subregister means that the
whole register is live-in. It is equivalent to a full mask.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp?rev=300335&r1=300334&r2=300335&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp Fri Apr 14 11:21:55 2017
@@ -232,14 +232,16 @@ HexagonBlockRanges::RegisterSet HexagonB
       const TargetRegisterInfo &TRI) {
   RegisterSet LiveIns;
   RegisterSet Tmp;
+
   for (auto I : B.liveins()) {
-    if (I.LaneMask.all()) {
-      Tmp.insert({I.PhysReg,0});
+    MCSubRegIndexIterator S(I.PhysReg, &TRI);
+    if (I.LaneMask.all() || (I.LaneMask.any() && !S.isValid())) {
+      Tmp.insert({I.PhysReg, 0});
       continue;
     }
-    for (MCSubRegIndexIterator S(I.PhysReg, &TRI); S.isValid(); ++S) {
-      LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
-      if ((M & I.LaneMask).any())
+    for (; S.isValid(); ++S) {
+      unsigned SI = S.getSubRegIndex();
+      if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any())
         Tmp.insert({S.getSubReg(), 0});
     }
   }