[PATCH] D31993: [AMDGPU] Combine DS operations with offsets bigger than byte

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:387-389
+    *BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::V_ADD_I32_e32), BaseReg)
+                        .addImm(CI.BaseOff)
+                        .addReg(AddrReg->getReg());
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rampitec wrote:
> rampitec wrote:
> > arsenm wrote:
> > > This should use the e64 version with an unused carry. We should add a helper to TII to emit this since it will change with GFX9
> > Matt, I doubt we should use e64 version here. It does not accept immediate, which effectively would require one more SGPR and one more mov. A vcc thrashing seems to be less issue.
> Even new no-carry variant is VOP3, so same issue.
You can materialize the constant in a register. It will be folded and shrunk later


Repository:
  rL LLVM

https://reviews.llvm.org/D31993