[PATCH] D31993: [AMDGPU] Combine DS operations with offsets bigger than byte

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin accepted this revision.
vpykhtin added inline comments.
This revision is now accepted and ready to land.


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Comment at: lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:78
+    unsigned Offset1;
+    unsigned BaseOff;
+    bool UseST64;
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rampitec wrote:
> vpykhtin wrote:
> > rampitec wrote:
> > > vpykhtin wrote:
> > > > Why 3 offsets?
> > > Two offsets as it will be encoded into an LDS instruction, and then base offset which needs to be added with v_add_i32 to the pointer if non zero.
> > But one of it would become zero in the instruction?
> For now yes, either Offset0 or BaseOff are zero.
> 
> In a longer term that is not necessarily so. Imagine you could add less to the base pointer, use both offsets in the encoding, and then reuse new base register for another couple of registers, where this code will generate a separate v_add_i32 otherwise.
Right.


Repository:
  rL LLVM

https://reviews.llvm.org/D31993