[PATCH] D32018: [MVT][SVE] Scalable vector MVTs (2/3)

[Renato Golin via Phabricator via llvm-commits]

rengolin added inline comments.


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Comment at: include/llvm/CodeGen/MachineValueType.h:144
+
+      v2f16          =  81,   //  2 x f16
+      v4f16          =  82,   //  4 x f16
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Are these values serialised in binary IR form?

If so, then reading previous IR would give you the wrong types, no?


https://reviews.llvm.org/D32018