[PATCH] D31965: [SLP] Enable 64-bit wide vectorization for Cyclone

[Renato Golin via Phabricator via llvm-commits]

rengolin added a reviewer: kristof.beyls.
rengolin added a subscriber: kristof.beyls.
rengolin added a comment.

Hi Adam,

Interesting results! But it doesn't sound like this is Cyclone specific.

@kristof.beyls Can you check on A57?

cheers,
--renato



================
Comment at: include/llvm/Analysis/TargetTransformInfoImpl.h:306
 
+  unsigned getMinVectorRegisterBitWidth() { return 128; }
+
----------------
Is this value really the best default to all targets?


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Comment at: lib/Target/AArch64/AArch64Subtarget.cpp:62
     MaxPrefetchIterationsAhead = 3;
+    // Enable 64-bit vectorization in SLP.
+    MinVectorRegisterBitWidth = 64;
----------------
Is this really Cyclone specific? ?Have you benchmarked on other cores?


https://reviews.llvm.org/D31965