[llvm] r299994 - [AArch64] Fix scheduling info for INS(vector, general) instruction.

[Balaram Makam via llvm-commits]

Author: bmakam
Date: Tue Apr 11 17:14:10 2017
New Revision: 299994

URL: http://llvm.org/viewvc/llvm-project?rev=299994&view=rev
Log:
[AArch64] Fix scheduling info for INS(vector, general) instruction.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td?rev=299994&r1=299993&r2=299994&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorDetails.td Tue Apr 11 17:14:10 2017
@@ -292,8 +292,8 @@ def : InstRW<[FalkorWr_1VXVY_5cyc],   (i
 
 def : InstRW<[FalkorWr_1VXVY_6cyc],   (instrs FRECPS64, FRSQRTS64)>;
 
+def : InstRW<[FalkorWr_1GTOV_1VXVY_2cyc],(instregex "^INSv(i32|i64)(gpr|lane)$")>;
 def : InstRW<[FalkorWr_2GTOV_1cyc],   (instregex "^DUP(v4i32|v2i64)(gpr|lane)$")>;
-def : InstRW<[FalkorWr_2GTOV_1cyc],   (instregex "^INSv(i32|i64)(gpr|lane)$")>;
 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instrs EXTv16i8)>;
 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instregex "(MOVI|MVNI)(v2d_ns|v16b_ns|v4i32|v8i16|v4s_msl)$")>;
 def : InstRW<[FalkorWr_2VXVY_1cyc],   (instrs NOTv16i8)>;

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td?rev=299994&r1=299993&r2=299994&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td Tue Apr 11 17:14:10 2017
@@ -118,6 +118,11 @@ def FalkorWr_1VX_1VY_10cyc : SchedWriteR
   let NumMicroOps = 2;
 }
 
+def FalkorWr_1GTOV_1VXVY_2cyc : SchedWriteRes<[FalkorUnitGTOV, FalkorUnitVXVY]> {
+  let Latency = 2;
+  let NumMicroOps = 2;
+}
+
 def FalkorWr_2GTOV_1cyc    : SchedWriteRes<[FalkorUnitGTOV, FalkorUnitGTOV]> {
   let Latency = 1;
   let NumMicroOps = 2;