[PATCH] D31958: [Hexagon] Switch to parametrized register classes for HVX
Krzysztof Parzyszek via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 11 14:14:22 PDT 2017
kparzysz created this revision.
This removes the 128-byte instruction set. Single instruction set works for both modes.
Repository:
rL LLVM
https://reviews.llvm.org/D31958
Files:
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
lib/Target/Hexagon/Hexagon.td
lib/Target/Hexagon/HexagonAsmPrinter.cpp
lib/Target/Hexagon/HexagonBitSimplify.cpp
lib/Target/Hexagon/HexagonBitTracker.cpp
lib/Target/Hexagon/HexagonCopyToCombine.cpp
lib/Target/Hexagon/HexagonDepInstrFormats.td
lib/Target/Hexagon/HexagonDepInstrInfo.td
lib/Target/Hexagon/HexagonDepMappings.td
lib/Target/Hexagon/HexagonEarlyIfConv.cpp
lib/Target/Hexagon/HexagonExpandCondsets.cpp
lib/Target/Hexagon/HexagonFrameLowering.cpp
lib/Target/Hexagon/HexagonHardwareLoops.cpp
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
lib/Target/Hexagon/HexagonISelLowering.cpp
lib/Target/Hexagon/HexagonInstrInfo.cpp
lib/Target/Hexagon/HexagonInstrInfo.h
lib/Target/Hexagon/HexagonIntrinsics.td
lib/Target/Hexagon/HexagonIntrinsicsV60.td
lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td
lib/Target/Hexagon/HexagonPatterns.td
lib/Target/Hexagon/HexagonPseudo.td
lib/Target/Hexagon/HexagonRegisterInfo.cpp
lib/Target/Hexagon/HexagonRegisterInfo.h
lib/Target/Hexagon/HexagonRegisterInfo.td
lib/Target/Hexagon/HexagonSubtarget.cpp
lib/Target/Hexagon/HexagonSubtarget.h
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
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