[PATCH] D31951: TableGen support for parametrized register class information

[Krzysztof Parzyszek via Phabricator via llvm-commits]

kparzysz added a comment.

Each HW mode is defined via a set of subtarget features (that need to be either enabled or disabled).  Since the mode serves as a predicate for the generated patterns, the check for subtarget features has to take place in the same context as Predicate checks for the usual pattern predicated.  This context is the SelectionDAGISel, and to facilitate the feature check, the generated code calls a function "TargetSubtargetInfo::checkFeatures", which takes a feature string and returns a boolean value.

There is another patch on the way that implements the "checkFeatures" function in subtarget.

I don't like some of the names I used, but I didn't want to spend time thinking about the best possible names.  For example anything that starts with "Variable..." should probably have a better name.  The RegisterClass member VRI (in Target.td) should likely have a more descriptive name too.


Repository:
  rL LLVM

https://reviews.llvm.org/D31951