[llvm] r299964 - [AMDGPU] Add A5 to data layout for amdgiz environment

[Yaxun Liu via llvm-commits]

Author: yaxunl
Date: Tue Apr 11 12:18:13 2017
New Revision: 299964

URL: http://llvm.org/viewvc/llvm-project?rev=299964&view=rev
Log:
[AMDGPU] Add A5 to data layout for amdgiz environment

Differential Revision: https://reviews.llvm.org/D31589

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    llvm/trunk/test/CodeGen/AMDGPU/env-amdgiz.ll
    llvm/trunk/test/CodeGen/AMDGPU/env-amdgizcl.ll

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=299964&r1=299963&r2=299964&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Tue Apr 11 12:18:13 2017
@@ -214,7 +214,7 @@ static StringRef computeDataLayout(const
       TT.getEnvironmentName() == "amdgizcl")
     return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
-         "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
+         "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
   return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
       "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
       "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";

Modified: llvm/trunk/test/CodeGen/AMDGPU/env-amdgiz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/env-amdgiz.ll?rev=299964&r1=299963&r2=299964&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/env-amdgiz.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/env-amdgiz.ll Tue Apr 11 12:18:13 2017
@@ -1,7 +1,7 @@
 ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa-amdgiz -verify-machineinstrs < %s
 ; Just check the target feature and data layout is accepted without error.
 
-target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
 target triple = "amdgcn-amd-amdhsa-amdgiz"
 
 define void @foo() {

Modified: llvm/trunk/test/CodeGen/AMDGPU/env-amdgizcl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/env-amdgizcl.ll?rev=299964&r1=299963&r2=299964&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/env-amdgizcl.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/env-amdgizcl.ll Tue Apr 11 12:18:13 2017
@@ -1,7 +1,7 @@
 ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa-amdgizcl -verify-machineinstrs < %s
 ; Just check the target feature and data layout is accepted without error.
 
-target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
 target triple = "amdgcn-amd-amdhsa-amdgizcl"
 
 define void @foo() {