[llvm] r299929 - [GlobalISel] LegalizerInfo: Enable legalization of non-power-of-2 types
Volkan Keles via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 11 03:10:14 PDT 2017
Author: volkan
Date: Tue Apr 11 05:10:14 2017
New Revision: 299929
URL: http://llvm.org/viewvc/llvm-project?rev=299929&view=rev
Log:
[GlobalISel] LegalizerInfo: Enable legalization of non-power-of-2 types
Summary: Legalize only if the type is marked as Legal or Custom. If not, return Unsupported as LegalizerHelper is not able to handle non-power-of-2 types right now.
Reviewers: qcolombet, aditya_nandakumar, dsanders, t.p.northover, kristof.beyls, javed.absar, ab
Reviewed By: kristof.beyls, ab
Subscribers: dberris, rovka, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D31711
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp?rev=299929&r1=299928&r2=299929&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerInfo.cpp Tue Apr 11 05:10:14 2017
@@ -73,11 +73,6 @@ LegalizerInfo::getAction(const InstrAspe
// These *have* to be implemented for now, they're the fundamental basis of
// how everything else is transformed.
- // Nothing is going to go well with types that aren't a power of 2 yet, so
- // don't even try because we might make things worse.
- if (!isPowerOf2_64(Aspect.Type.getSizeInBits()))
- return std::make_pair(Unsupported, LLT());
-
// FIXME: the long-term plan calls for expansion in terms of load/store (if
// they're not legal).
if (Aspect.Opcode == TargetOpcode::G_SEQUENCE ||
@@ -86,12 +81,20 @@ LegalizerInfo::getAction(const InstrAspe
Aspect.Opcode == TargetOpcode::G_UNMERGE_VALUES)
return std::make_pair(Legal, Aspect.Type);
+ LLT Ty = Aspect.Type;
LegalizeAction Action = findInActions(Aspect);
+ // LegalizerHelper is not able to handle non-power-of-2 types right now, so do
+ // not try to legalize them unless they are marked as Legal or Custom.
+ // FIXME: This is a temporary hack until the general non-power-of-2
+ // legalization works.
+ if (!isPowerOf2_64(Ty.getSizeInBits()) &&
+ !(Action == Legal || Action == Custom))
+ return std::make_pair(Unsupported, LLT());
+
if (Action != NotFound)
return findLegalAction(Aspect, Action);
unsigned Opcode = Aspect.Opcode;
- LLT Ty = Aspect.Type;
if (!Ty.isVector()) {
auto DefaultAction = DefaultActions.find(Aspect.Opcode);
if (DefaultAction != DefaultActions.end() && DefaultAction->second == Legal)
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll?rev=299929&r1=299928&r2=299929&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll Tue Apr 11 05:10:14 2017
@@ -71,6 +71,14 @@ define void @odd_type(i42* %addr) {
ret void
}
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(<7 x s32>) = G_LOAD %vreg0; mem:LD28[%addr](align=32) (in function: odd_vector)
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector
+; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector:
+define void @odd_vector(<7 x i32>* %addr) {
+ %vec = load <7 x i32>, <7 x i32>* %addr
+ ret void
+}
+
; RegBankSelect crashed when given invalid mappings, and AArch64's
; implementation produce valid-but-nonsense mappings for G_SEQUENCE.
; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir?rev=299929&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir Tue Apr 11 05:10:14 2017
@@ -0,0 +1,29 @@
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64--"
+ define void @test_legalize_merge_v3s32() {
+ ret void
+ }
+...
+---
+name: test_legalize_merge_v3s32
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+body: |
+ bb.0:
+ liveins: %w0, %w1, %w2
+ ; CHECK-LABEL: name: test_legalize_merge_v3s32
+ ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
+ ; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %w1
+ ; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %w2
+ ; CHECK: (<3 x s32>) = G_MERGE_VALUES [[ARG1]](s32), [[ARG2]](s32), [[ARG3]](s32)
+ %0(s32) = COPY %w0
+ %1(s32) = COPY %w1
+ %2(s32) = COPY %w2
+ %3(<3 x s32>) = G_MERGE_VALUES %0(s32), %1(s32), %2(s32)
+...
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