[llvm] r299910 - [PowerPC] multiply-with-overflow might use the CTR register
Hal Finkel via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 10 19:03:17 PDT 2017
Author: hfinkel
Date: Mon Apr 10 21:03:17 2017
New Revision: 299910
URL: http://llvm.org/viewvc/llvm-project?rev=299910&view=rev
Log:
[PowerPC] multiply-with-overflow might use the CTR register
Check the legality of ISD::[US]MULO to see whether
Intrinsic::[us]mul_with_overflow will legalize into a function call (and, thus,
will use the CTR register). Fixes PR32485.
Patch by Tim Neumann!
Differential Revision: https://reviews.llvm.org/D31790
Added:
llvm/trunk/test/CodeGen/PowerPC/ctrloop-i128.ll
Modified:
llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp
Modified: llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp?rev=299910&r1=299909&r2=299910&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp Mon Apr 10 21:03:17 2017
@@ -298,15 +298,17 @@ bool PPCCTRLoops::mightUseCTR(const Trip
return true;
else
continue; // ISD::FCOPYSIGN is never a library call.
- case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
- case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
- case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
- case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
- case Intrinsic::rint: Opcode = ISD::FRINT; break;
- case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
- case Intrinsic::round: Opcode = ISD::FROUND; break;
- case Intrinsic::minnum: Opcode = ISD::FMINNUM; break;
- case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break;
+ case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
+ case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
+ case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
+ case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
+ case Intrinsic::rint: Opcode = ISD::FRINT; break;
+ case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
+ case Intrinsic::round: Opcode = ISD::FROUND; break;
+ case Intrinsic::minnum: Opcode = ISD::FMINNUM; break;
+ case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break;
+ case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break;
+ case Intrinsic::smul_with_overflow: Opcode = ISD::SMULO; break;
}
}
Added: llvm/trunk/test/CodeGen/PowerPC/ctrloop-i128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ctrloop-i128.ll?rev=299910&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ctrloop-i128.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/ctrloop-i128.ll Mon Apr 10 21:03:17 2017
@@ -0,0 +1,34 @@
+; RUN: llc -O1 -verify-machineinstrs < %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: uwtable
+define fastcc void @_Crash_Fn() unnamed_addr #0 {
+entry-block:
+ br label %_Label_0
+
+_Label_0: ; preds = %_Label_0, %entry-block
+ %result.0138 = phi i128 [ %5, %_Label_0 ], [ 0, %entry-block ]
+ %iter.sroa.0.0137 = phi i8* [ %0, %_Label_0 ], [ undef, %entry-block ]
+ %0 = getelementptr inbounds i8, i8* %iter.sroa.0.0137, i64 1
+ %1 = tail call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %result.0138, i128 undef) #2
+ %2 = extractvalue { i128, i1 } %1, 0
+ %3 = tail call { i128, i1 } @llvm.sadd.with.overflow.i128(i128 %2, i128 0) #2
+ %4 = extractvalue { i128, i1 } %3, 1
+ %5 = extractvalue { i128, i1 } %3, 0
+ %6 = icmp eq i8* %0, null
+ br i1 %6, label %bb66.loopexit, label %_Label_0
+
+bb66.loopexit: ; preds = %_Label_0
+ unreachable
+}
+
+; Function Attrs: nounwind readnone
+declare { i128, i1 } @llvm.sadd.with.overflow.i128(i128, i128) #1
+
+; Function Attrs: nounwind readnone
+declare { i128, i1 } @llvm.smul.with.overflow.i128(i128, i128) #1
+
+attributes #0 = { uwtable }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
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