[PATCH] D31783: Move size and alignment information of regclass to TargetRegisterInfo

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added a comment.

While doing these changes in the API for fetching the sizes (getRegSize and getSpillSize) it would be interesting to at the same time considering to at least change getRegSize to return size in bits, but maybe also the getSpillSize.
The spillSize must be a multiple of the byte size, but there are targets where the register size in bits isn't a multiple of the byte size (e.g. 1-bit registers). So don't we need to be able to express the register size in bits?

The interface could ofcourse also provide methods for fetching the sizes in either bits or bytes:

  getRegSizeInBits()
  getRegSize()   // In bytes, rounded up? Or down? Maybe call this getRegSizeInBytes()?
  getSpillSizeInBits()
  getSpillSize()  // In bytes

This would also get rid of some "getRegSize() *8" etc in the code, perhaps making the code easier to read (you do not need to know

As a side note our out-of-tree target has 16-bit bytes (which I think could be common for several other DSP targets etc). 
And we have 24-bit and 40 bit registers (that aren't a multiple of the byte size).
And we have patches all over the place to replace (x * 8) and (x / 8) by something where we can toggle byte size depending on target.
I do not expect changes making the code more complicated just to support out-of-tree-targets, but if it isn't a big cost to make the code a little bit more general (and for example hiding those magic "8" constants in a common accessor methods), then I think it could be of great help for other targets also.


Repository:
  rL LLVM

https://reviews.llvm.org/D31783