[PATCH] D31872: AMDGPU: Minor SReg64 register class refactoring

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

I think this requires changing the register class for SSrc_32/VSrc_32 to be the one that includes the special 32-bit regs. I think I started doing this to start supporting vccz and the other special 1-bit inputs


https://reviews.llvm.org/D31872