[PATCH] D31715: [SelectionDAG] TargetLowering::SimplifyDemandedBits how to properly calculate KnownZero bits for ISD::SETCC and ISD::AssertZExt

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL299839: [SelectionDAG] TargetLowering::SimplifyDemandedBits how to properly calculate… (authored by ctopper).

Changed prior to commit:
  https://reviews.llvm.org/D31715?vs=94268&id=94645#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D31715

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp


Index: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -791,6 +791,10 @@
       // TODO: Should we check for other forms of sign-bit comparisons?
       // Examples: X <= -1, X >= 0
     }
+    if (getBooleanContents(Op0.getValueType()) ==
+            TargetLowering::ZeroOrOneBooleanContent &&
+        BitWidth > 1)
+      KnownZero.setBitsFrom(1);
     break;
   }
   case ISD::SHL:
@@ -1233,7 +1237,7 @@
       return true;
     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
 
-    KnownZero |= ~InMask & NewMask;
+    KnownZero |= ~InMask;
     break;
   }
   case ISD::BITCAST:


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