[PATCH] D31817: [ARM/AArch64] Ensure valid vector element types for interleaved accesses

[Matthew Simpson via Phabricator via llvm-commits]

mssimpso added a comment.

Thanks Chad!



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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7264
+  // 128 will be split into multiple interleaved accesses.
+  if (VecSize != 64 && VecSize % 128 != 0)
+    return false;
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mcrosier wrote:
>   return VecSize == 64 || VecSize % 128 == 0;
Ah, nice catch!


https://reviews.llvm.org/D31817