[llvm] r299757 - [AMDGPU] Move SiShrinkInstruction and SDWAPeephole to SSAOptimization passes

[Sam Kolton via llvm-commits]

Author: skolton
Date: Fri Apr  7 05:53:12 2017
New Revision: 299757

URL: http://llvm.org/viewvc/llvm-project?rev=299757&view=rev
Log:
[AMDGPU] Move SiShrinkInstruction and SDWAPeephole to SSAOptimization passes

Summary:
Difference beetween PreRegAlloc() and MachineSSAOptimization() are that the former is run despite of -O0 optimization level. In my undestanding SiShrinkInstructions and SDWAPeephole shouldn't run when optimizations are disabled.
With this change order of passes will not change.

Reviewers: arsenm, vpykhtin, rampitec

Subscribers: qcolombet, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D31705

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    llvm/trunk/test/CodeGen/AMDGPU/llvm.dbg.value.ll
    llvm/trunk/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=299757&r1=299756&r2=299757&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Fri Apr  7 05:53:12 2017
@@ -716,6 +716,11 @@ void GCNPassConfig::addMachineSSAOptimiz
   addPass(&SIFoldOperandsID);
   addPass(&DeadMachineInstructionElimID);
   addPass(&SILoadStoreOptimizerID);
+  addPass(createSIShrinkInstructionsPass());
+  if (EnableSDWAPeephole) {
+    addPass(&SIPeepholeSDWAID);
+    addPass(&DeadMachineInstructionElimID);
+  }
 }
 
 bool GCNPassConfig::addILPOpts() {
@@ -757,11 +762,6 @@ bool GCNPassConfig::addGlobalInstruction
 #endif
 
 void GCNPassConfig::addPreRegAlloc() {
-  addPass(createSIShrinkInstructionsPass());
-  if (EnableSDWAPeephole) {
-    addPass(&SIPeepholeSDWAID);
-    addPass(&DeadMachineInstructionElimID);
-  }
   addPass(createSIWholeQuadModePass());
 }
 

Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.dbg.value.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.dbg.value.ll?rev=299757&r1=299756&r2=299757&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.dbg.value.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.dbg.value.ll Fri Apr  7 05:53:12 2017
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -amdgpu-sdwa-peephole=0 -verify-machineinstrs -mattr=-flat-for-global < %s | FileCheck %s
+; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs -mattr=-flat-for-global < %s | FileCheck %s
 
 ; CHECK-LABEL: {{^}}test_debug_value:
 ; CHECK: s_load_dwordx2 s[4:5]

Modified: llvm/trunk/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll?rev=299757&r1=299756&r2=299757&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll Fri Apr  7 05:53:12 2017
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -march=amdgcn -mcpu=hawaii -amdgpu-sdwa-peephole=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR -check-prefix=GCN %s
+; RUN: llc -O0 -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR -check-prefix=GCN %s
 
 ; FIXME: we should disable sdwa peephole because dead-code elimination, that
 ; runs after peephole, ruins this test (different register numbers)