[llvm] r299688 - [SDAG] Fix visitAND optimization to deal with vector extract case again.

[Nirav Dave via llvm-commits]

Author: niravd
Date: Thu Apr  6 14:05:41 2017
New Revision: 299688

URL: http://llvm.org/viewvc/llvm-project?rev=299688&view=rev
Log:
[SDAG] Fix visitAND optimization to deal with vector extract case again.

Summary:
Fix case elided by rL298920.

Fixes PR32545.

Reviewers: eli.friedman, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31759

Added:
    llvm/trunk/test/CodeGen/ARM/pr32545.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=299688&r1=299687&r2=299688&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Apr  6 14:05:41 2017
@@ -3589,7 +3589,7 @@ SDValue DAGCombiner::visitAND(SDNode *N)
       SDValue NewLoad(Load, 0);
 
       // Fold the AND away. NewLoad may get replaced immediately.
-      CombineTo(N, NewLoad);
+      CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
 
       if (Load->getExtensionType() == ISD::EXTLOAD) {
         NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,

Added: llvm/trunk/test/CodeGen/ARM/pr32545.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/pr32545.ll?rev=299688&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/pr32545.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/pr32545.ll Thu Apr  6 14:05:41 2017
@@ -0,0 +1,22 @@
+; RUN: llc %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7--linux-gnueabi"
+
+; CHECK: vld1.16	{[[DREG:d[0-9]+]][0]}, {{.*}}
+; CHECK: vmovl.u8	[[QREG:q[0-9]+]], [[DREG]]
+; CHECK: vmovl.u16	[[QREG]], [[DREG]]
+
+define void @f(i32 %dstStride, i8* %indvars.iv, <2 x i8>* %zz) {
+entry:
+  br label %for.body
+
+for.body:
+  %tmp = load <2 x i8>, <2 x i8>* %zz, align 1
+  %tmp1 = extractelement <2 x i8> %tmp, i32 0
+  %.lhs.rhs = zext i8 %tmp1 to i32
+  call void @g(i32 %.lhs.rhs)
+  br label %for.body
+}
+
+declare void @g(i32)