[llvm] r299664 - [Hexagon] Change the vector scaling for vector offsets
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 6 10:28:22 PDT 2017
Author: kparzysz
Date: Thu Apr 6 12:28:21 2017
New Revision: 299664
URL: http://llvm.org/viewvc/llvm-project?rev=299664&view=rev
Log:
[Hexagon] Change the vector scaling for vector offsets
Keep full offset value on MI-level instructions, but have it scaled down
in the MC-level instructions.
Modified:
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h
llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td
llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td
llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=299664&r1=299663&r2=299664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Thu Apr 6 12:28:21 2017
@@ -320,10 +320,6 @@ public:
bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
- bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); }
- bool iss4_7Imm() const { return CheckImmRange(4, 0, true, false, false); }
- bool iss3_7Imm() const { return CheckImmRange(3, 0, true, false, false); }
- bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); }
bool iss3_0Imm() const { return CheckImmRange(3, 0, true, false, false); }
bool isu64_0Imm() const { return CheckImmRange(64, 0, false, true, true); }
@@ -406,20 +402,6 @@ public:
addImmOperands(Inst, N);
}
- void adds4_6ImmOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *CE =
- dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm()));
- Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
- }
-
- void adds3_6ImmOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCConstantExpr *CE =
- dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm()));
- Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
- }
-
StringRef getToken() const {
assert(Kind == Token && "Invalid access!");
return StringRef(Tok.Data, Tok.Length);
Modified: llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=299664&r1=299663&r2=299664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp Thu Apr 6 12:28:21 2017
@@ -148,9 +148,7 @@ static DecodeStatus s4_2ImmDecoder(MCIns
const void *Decoder);
static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const void *Decoder);
-static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
- const void *Decoder);
-static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
+static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const void *Decoder);
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
const void *Decoder);
@@ -631,18 +629,6 @@ static DecodeStatus unsignedImmDecoder(M
return MCDisassembler::Success;
}
-static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp,
- uint64_t /*Address*/, const void *Decoder) {
- signedDecoder<10>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-
-static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp,
- uint64_t /*Address*/, const void *Decoder) {
- signedDecoder<19>(MI, tmp, Decoder);
- return MCDisassembler::Success;
-}
-
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
uint64_t /*Address*/, const void *Decoder) {
HexagonDisassembler const &Disassembler = disassembler(Decoder);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=299664&r1=299663&r2=299664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Thu Apr 6 12:28:21 2017
@@ -261,10 +261,34 @@ static MCSymbol *smallData(AsmPrinter &A
return Sym;
}
+static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
+ unsigned VectorSize, MCContext &Ctx) {
+ MCInst T;
+ T.setOpcode(Inst.getOpcode());
+ for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) {
+ if (i != OpNo) {
+ T.addOperand(Inst.getOperand(i));
+ continue;
+ }
+ MCOperand &ImmOp = Inst.getOperand(i);
+ const auto *HE = static_cast<const HexagonMCExpr*>(ImmOp.getExpr());
+ int32_t V = cast<MCConstantExpr>(HE->getExpr())->getValue();
+ auto *NewCE = MCConstantExpr::create(V / int32_t(VectorSize), Ctx);
+ auto *NewHE = HexagonMCExpr::create(NewCE, Ctx);
+ T.addOperand(MCOperand::createExpr(NewHE));
+ }
+ return T;
+}
+
void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
const MachineInstr &MI) {
MCInst &MappedInst = static_cast <MCInst &>(Inst);
const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
+ const MachineFunction &MF = *MI.getParent()->getParent();
+ const auto &HST = MF.getSubtarget<HexagonSubtarget>();
+ unsigned VectorSize = HST.useHVXSglOps()
+ ? Hexagon::VectorRegsRegClass.getSize()
+ : Hexagon::VectorRegs128BRegClass.getSize();
switch (Inst.getOpcode()) {
default: return;
@@ -597,6 +621,181 @@ void HexagonAsmPrinter::HexagonProcessIn
return;
}
+ case Hexagon::V6_vL32Ub_pi:
+ case Hexagon::V6_vL32b_cur_pi:
+ case Hexagon::V6_vL32b_nt_cur_pi:
+ case Hexagon::V6_vL32b_pi:
+ case Hexagon::V6_vL32b_nt_pi:
+ case Hexagon::V6_vL32b_nt_tmp_pi:
+ case Hexagon::V6_vL32b_tmp_pi:
+ case Hexagon::V6_vL32Ub_pi_128B:
+ case Hexagon::V6_vL32b_cur_pi_128B:
+ case Hexagon::V6_vL32b_nt_cur_pi_128B:
+ case Hexagon::V6_vL32b_pi_128B:
+ case Hexagon::V6_vL32b_nt_pi_128B:
+ case Hexagon::V6_vL32b_nt_tmp_pi_128B:
+ case Hexagon::V6_vL32b_tmp_pi_128B:
+ MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
+ return;
+
+ case Hexagon::V6_vL32Ub_ai:
+ case Hexagon::V6_vL32b_ai:
+ case Hexagon::V6_vL32b_cur_ai:
+ case Hexagon::V6_vL32b_nt_ai:
+ case Hexagon::V6_vL32b_nt_cur_ai:
+ case Hexagon::V6_vL32b_nt_tmp_ai:
+ case Hexagon::V6_vL32b_tmp_ai:
+ case Hexagon::V6_vL32Ub_ai_128B:
+ case Hexagon::V6_vL32b_ai_128B:
+ case Hexagon::V6_vL32b_cur_ai_128B:
+ case Hexagon::V6_vL32b_nt_ai_128B:
+ case Hexagon::V6_vL32b_nt_cur_ai_128B:
+ case Hexagon::V6_vL32b_nt_tmp_ai_128B:
+ case Hexagon::V6_vL32b_tmp_ai_128B:
+ MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
+ return;
+
+ case Hexagon::V6_vS32Ub_pi:
+ case Hexagon::V6_vS32b_new_pi:
+ case Hexagon::V6_vS32b_nt_new_pi:
+ case Hexagon::V6_vS32b_nt_pi:
+ case Hexagon::V6_vS32b_pi:
+ case Hexagon::V6_vS32Ub_pi_128B:
+ case Hexagon::V6_vS32b_new_pi_128B:
+ case Hexagon::V6_vS32b_nt_new_pi_128B:
+ case Hexagon::V6_vS32b_nt_pi_128B:
+ case Hexagon::V6_vS32b_pi_128B:
+ MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
+ return;
+
+ case Hexagon::V6_vS32Ub_ai:
+ case Hexagon::V6_vS32b_ai:
+ case Hexagon::V6_vS32b_new_ai:
+ case Hexagon::V6_vS32b_nt_ai:
+ case Hexagon::V6_vS32b_nt_new_ai:
+ case Hexagon::V6_vS32Ub_ai_128B:
+ case Hexagon::V6_vS32b_ai_128B:
+ case Hexagon::V6_vS32b_new_ai_128B:
+ case Hexagon::V6_vS32b_nt_ai_128B:
+ case Hexagon::V6_vS32b_nt_new_ai_128B:
+ MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
+ return;
+
+ case Hexagon::V6_vL32b_cur_npred_pi:
+ case Hexagon::V6_vL32b_cur_pred_pi:
+ case Hexagon::V6_vL32b_npred_pi:
+ case Hexagon::V6_vL32b_nt_cur_npred_pi:
+ case Hexagon::V6_vL32b_nt_cur_pred_pi:
+ case Hexagon::V6_vL32b_nt_npred_pi:
+ case Hexagon::V6_vL32b_nt_pred_pi:
+ case Hexagon::V6_vL32b_nt_tmp_npred_pi:
+ case Hexagon::V6_vL32b_nt_tmp_pred_pi:
+ case Hexagon::V6_vL32b_pred_pi:
+ case Hexagon::V6_vL32b_tmp_npred_pi:
+ case Hexagon::V6_vL32b_tmp_pred_pi:
+ case Hexagon::V6_vL32b_cur_npred_pi_128B:
+ case Hexagon::V6_vL32b_cur_pred_pi_128B:
+ case Hexagon::V6_vL32b_npred_pi_128B:
+ case Hexagon::V6_vL32b_nt_cur_npred_pi_128B:
+ case Hexagon::V6_vL32b_nt_cur_pred_pi_128B:
+ case Hexagon::V6_vL32b_nt_npred_pi_128B:
+ case Hexagon::V6_vL32b_nt_pred_pi_128B:
+ case Hexagon::V6_vL32b_nt_tmp_npred_pi_128B:
+ case Hexagon::V6_vL32b_nt_tmp_pred_pi_128B:
+ case Hexagon::V6_vL32b_pred_pi_128B:
+ case Hexagon::V6_vL32b_tmp_npred_pi_128B:
+ case Hexagon::V6_vL32b_tmp_pred_pi_128B:
+ MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext);
+ return;
+
+ case Hexagon::V6_vL32b_cur_npred_ai:
+ case Hexagon::V6_vL32b_cur_pred_ai:
+ case Hexagon::V6_vL32b_npred_ai:
+ case Hexagon::V6_vL32b_nt_cur_npred_ai:
+ case Hexagon::V6_vL32b_nt_cur_pred_ai:
+ case Hexagon::V6_vL32b_nt_npred_ai:
+ case Hexagon::V6_vL32b_nt_pred_ai:
+ case Hexagon::V6_vL32b_nt_tmp_npred_ai:
+ case Hexagon::V6_vL32b_nt_tmp_pred_ai:
+ case Hexagon::V6_vL32b_pred_ai:
+ case Hexagon::V6_vL32b_tmp_npred_ai:
+ case Hexagon::V6_vL32b_tmp_pred_ai:
+ case Hexagon::V6_vL32b_cur_npred_ai_128B:
+ case Hexagon::V6_vL32b_cur_pred_ai_128B:
+ case Hexagon::V6_vL32b_npred_ai_128B:
+ case Hexagon::V6_vL32b_nt_cur_npred_ai_128B:
+ case Hexagon::V6_vL32b_nt_cur_pred_ai_128B:
+ case Hexagon::V6_vL32b_nt_npred_ai_128B:
+ case Hexagon::V6_vL32b_nt_pred_ai_128B:
+ case Hexagon::V6_vL32b_nt_tmp_npred_ai_128B:
+ case Hexagon::V6_vL32b_nt_tmp_pred_ai_128B:
+ case Hexagon::V6_vL32b_pred_ai_128B:
+ case Hexagon::V6_vL32b_tmp_npred_ai_128B:
+ case Hexagon::V6_vL32b_tmp_pred_ai_128B:
+ MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
+ return;
+
+ case Hexagon::V6_vS32Ub_npred_pi:
+ case Hexagon::V6_vS32Ub_pred_pi:
+ case Hexagon::V6_vS32b_new_npred_pi:
+ case Hexagon::V6_vS32b_new_pred_pi:
+ case Hexagon::V6_vS32b_npred_pi:
+ case Hexagon::V6_vS32b_nqpred_pi:
+ case Hexagon::V6_vS32b_nt_new_npred_pi:
+ case Hexagon::V6_vS32b_nt_new_pred_pi:
+ case Hexagon::V6_vS32b_nt_npred_pi:
+ case Hexagon::V6_vS32b_nt_nqpred_pi:
+ case Hexagon::V6_vS32b_nt_pred_pi:
+ case Hexagon::V6_vS32b_nt_qpred_pi:
+ case Hexagon::V6_vS32b_pred_pi:
+ case Hexagon::V6_vS32b_qpred_pi:
+ case Hexagon::V6_vS32Ub_npred_pi_128B:
+ case Hexagon::V6_vS32Ub_pred_pi_128B:
+ case Hexagon::V6_vS32b_new_npred_pi_128B:
+ case Hexagon::V6_vS32b_new_pred_pi_128B:
+ case Hexagon::V6_vS32b_npred_pi_128B:
+ case Hexagon::V6_vS32b_nqpred_pi_128B:
+ case Hexagon::V6_vS32b_nt_new_npred_pi_128B:
+ case Hexagon::V6_vS32b_nt_new_pred_pi_128B:
+ case Hexagon::V6_vS32b_nt_npred_pi_128B:
+ case Hexagon::V6_vS32b_nt_nqpred_pi_128B:
+ case Hexagon::V6_vS32b_nt_pred_pi_128B:
+ case Hexagon::V6_vS32b_nt_qpred_pi_128B:
+ case Hexagon::V6_vS32b_pred_pi_128B:
+ case Hexagon::V6_vS32b_qpred_pi_128B:
+ MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
+ return;
+
+ case Hexagon::V6_vS32Ub_npred_ai:
+ case Hexagon::V6_vS32Ub_pred_ai:
+ case Hexagon::V6_vS32b_new_npred_ai:
+ case Hexagon::V6_vS32b_new_pred_ai:
+ case Hexagon::V6_vS32b_npred_ai:
+ case Hexagon::V6_vS32b_nqpred_ai:
+ case Hexagon::V6_vS32b_nt_new_npred_ai:
+ case Hexagon::V6_vS32b_nt_new_pred_ai:
+ case Hexagon::V6_vS32b_nt_npred_ai:
+ case Hexagon::V6_vS32b_nt_nqpred_ai:
+ case Hexagon::V6_vS32b_nt_pred_ai:
+ case Hexagon::V6_vS32b_nt_qpred_ai:
+ case Hexagon::V6_vS32b_pred_ai:
+ case Hexagon::V6_vS32b_qpred_ai:
+ case Hexagon::V6_vS32Ub_npred_ai_128B:
+ case Hexagon::V6_vS32Ub_pred_ai_128B:
+ case Hexagon::V6_vS32b_new_npred_ai_128B:
+ case Hexagon::V6_vS32b_new_pred_ai_128B:
+ case Hexagon::V6_vS32b_npred_ai_128B:
+ case Hexagon::V6_vS32b_nqpred_ai_128B:
+ case Hexagon::V6_vS32b_nt_new_npred_ai_128B:
+ case Hexagon::V6_vS32b_nt_new_pred_ai_128B:
+ case Hexagon::V6_vS32b_nt_npred_ai_128B:
+ case Hexagon::V6_vS32b_nt_nqpred_ai_128B:
+ case Hexagon::V6_vS32b_nt_pred_ai_128B:
+ case Hexagon::V6_vS32b_nt_qpred_ai_128B:
+ case Hexagon::V6_vS32b_pred_ai_128B:
+ case Hexagon::V6_vS32b_qpred_ai_128B:
+ MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
+ return;
}
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h?rev=299664&r1=299663&r2=299664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepDecoders.h Thu Apr 6 12:28:21 2017
@@ -32,6 +32,11 @@ static DecodeStatus s31_1ImmDecoder(MCIn
signedDecoder<12>(MI, tmp, Decoder);
return MCDisassembler::Success;
}
+static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp,
+ uint64_t, const void *Decoder) {
+ signedDecoder<3>(MI, tmp, Decoder);
+ return MCDisassembler::Success;
+}
static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp,
uint64_t, const void *Decoder) {
signedDecoder<13>(MI, tmp, Decoder);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td?rev=299664&r1=299663&r2=299664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepInstrFormats.td Thu Apr 6 12:28:21 2017
@@ -28,8 +28,8 @@ class Enc_16626097 : OpcodeHexagon {
let Inst{4-0} = Vw32{4-0};
}
class Enc_13397056 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{10-8} = Ii{9-7};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <2> Qv4;
let Inst{12-11} = Qv4{1-0};
bits <5> Vs32;
@@ -49,15 +49,6 @@ class Enc_7315939 : OpcodeHexagon {
let Inst{13-13} = n1{1-1};
let Inst{8-8} = n1{0-0};
}
-class Enc_605928 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{13-13} = Ii{9-9};
- let Inst{10-8} = Ii{8-6};
- bits <5> Rt32;
- let Inst{20-16} = Rt32{4-0};
- bits <5> Zdd8;
- let Inst{4-0} = Zdd8{4-0};
-}
class Enc_15275738 : OpcodeHexagon {
bits <12> Ii;
let Inst{26-25} = Ii{11-10};
@@ -231,15 +222,6 @@ class Enc_1971351 : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
-class Enc_12373826 : OpcodeHexagon {
- bits <11> Ii;
- let Inst{13-13} = Ii{10-10};
- let Inst{10-8} = Ii{9-7};
- bits <5> Rt32;
- let Inst{20-16} = Rt32{4-0};
- bits <5> Zdd8;
- let Inst{4-0} = Zdd8{4-0};
-}
class Enc_13715847 : OpcodeHexagon {
bits <6> Ii;
let Inst{17-16} = Ii{5-4};
@@ -315,23 +297,6 @@ class Enc_10492541 : OpcodeHexagon {
}
class Enc_0 : OpcodeHexagon {
}
-class Enc_8868098 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{21-21} = Ii{9-9};
- let Inst{13-8} = Ii{8-3};
- let Inst{2-0} = Ii{2-0};
- bits <5> Vss32;
- let Inst{7-3} = Vss32{4-0};
- bits <5> Rx32;
- let Inst{20-16} = Rx32{4-0};
-}
-class Enc_10380392 : OpcodeHexagon {
- bits <11> Ii;
- let Inst{13-13} = Ii{10-10};
- let Inst{10-8} = Ii{9-7};
- bits <5> Rt32;
- let Inst{20-16} = Rt32{4-0};
-}
class Enc_15733946 : OpcodeHexagon {
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
@@ -343,9 +308,9 @@ class Enc_15733946 : OpcodeHexagon {
let Inst{20-16} = Rx32{4-0};
}
class Enc_738356 : OpcodeHexagon {
- bits <11> Ii;
- let Inst{13-13} = Ii{10-10};
- let Inst{10-8} = Ii{9-7};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <5> Rt32;
@@ -353,14 +318,6 @@ class Enc_738356 : OpcodeHexagon {
bits <5> Vd32;
let Inst{4-0} = Vd32{4-0};
}
-class Enc_15578334 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{10-8} = Ii{9-7};
- bits <5> Zdd8;
- let Inst{4-0} = Zdd8{4-0};
- bits <5> Rx32;
- let Inst{20-16} = Rx32{4-0};
-}
class Enc_14400220 : OpcodeHexagon {
bits <5> Ii;
let Inst{9-5} = Ii{4-0};
@@ -425,9 +382,9 @@ class Enc_14620934 : OpcodeHexagon {
let Inst{12-8} = Rt32{4-0};
}
class Enc_10075393 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{13-13} = Ii{9-9};
- let Inst{10-8} = Ii{8-6};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <5> Rt32;
@@ -927,8 +884,8 @@ class Enc_9305257 : OpcodeHexagon {
let Inst{4-0} = Vd32{4-0};
}
class Enc_3735566 : OpcodeHexagon {
- bits <9> Ii;
- let Inst{10-8} = Ii{8-6};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <3> Os8;
@@ -1033,9 +990,9 @@ class Enc_10263630 : OpcodeHexagon {
let Inst{7-3} = Vx32{4-0};
}
class Enc_13937564 : OpcodeHexagon {
- bits <11> Ii;
- let Inst{13-13} = Ii{10-10};
- let Inst{10-8} = Ii{9-7};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <5> Rt32;
@@ -1220,8 +1177,8 @@ class Enc_7912540 : OpcodeHexagon {
let Inst{4-0} = Rxx32{4-0};
}
class Enc_15560488 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{10-8} = Ii{9-7};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <5> Vd32;
@@ -1361,9 +1318,9 @@ class Enc_5636753 : OpcodeHexagon {
let Inst{20-16} = Vu32{4-0};
}
class Enc_5757366 : OpcodeHexagon {
- bits <11> Ii;
- let Inst{13-13} = Ii{10-10};
- let Inst{10-8} = Ii{9-7};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <5> Rt32;
let Inst{20-16} = Rt32{4-0};
bits <5> Vs32;
@@ -1421,9 +1378,9 @@ class Enc_9773189 : OpcodeHexagon {
let Inst{12-8} = Rxx32{4-0};
}
class Enc_2152247 : OpcodeHexagon {
- bits <11> Ii;
- let Inst{13-13} = Ii{10-10};
- let Inst{10-8} = Ii{9-7};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <5> Rt32;
let Inst{20-16} = Rt32{4-0};
bits <3> Os8;
@@ -1441,9 +1398,9 @@ class Enc_12848507 : OpcodeHexagon {
let Inst{12-8} = Rtt32{4-0};
}
class Enc_16279406 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{13-13} = Ii{9-9};
- let Inst{10-8} = Ii{8-6};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <2> Qv4;
let Inst{12-11} = Qv4{1-0};
bits <5> Rt32;
@@ -1499,8 +1456,8 @@ class Enc_4109168 : OpcodeHexagon {
let Inst{23-22} = Qv4{1-0};
}
class Enc_14560494 : OpcodeHexagon {
- bits <9> Ii;
- let Inst{10-8} = Ii{8-6};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <5> Vd32;
@@ -1532,8 +1489,8 @@ class Enc_11498120 : OpcodeHexagon {
let Inst{1-0} = Qd4{1-0};
}
class Enc_15459921 : OpcodeHexagon {
- bits <9> Ii;
- let Inst{10-8} = Ii{8-6};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <5> Vs32;
@@ -1777,9 +1734,9 @@ class Enc_48594 : OpcodeHexagon {
let Inst{20-16} = Rx32{4-0};
}
class Enc_6608821 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{13-13} = Ii{9-9};
- let Inst{10-8} = Ii{8-6};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <5> Rt32;
let Inst{20-16} = Rt32{4-0};
bits <3> Os8;
@@ -2003,19 +1960,13 @@ class Enc_16319737 : OpcodeHexagon {
let Inst{12-8} = Rtt32{4-0};
}
class Enc_2296022 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{10-8} = Ii{9-7};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <5> Vs32;
let Inst{4-0} = Vs32{4-0};
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
-class Enc_14546668 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{10-8} = Ii{9-7};
- bits <5> Rx32;
- let Inst{20-16} = Rx32{4-0};
-}
class Enc_9664427 : OpcodeHexagon {
bits <5> Vuu32;
let Inst{20-16} = Vuu32{4-0};
@@ -2249,9 +2200,9 @@ class Enc_13174858 : OpcodeHexagon {
let Inst{20-16} = Rx32{4-0};
}
class Enc_8437395 : OpcodeHexagon {
- bits <11> Ii;
- let Inst{13-13} = Ii{10-10};
- let Inst{10-8} = Ii{9-7};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <5> Rt32;
let Inst{20-16} = Rt32{4-0};
bits <5> Vd32;
@@ -2301,8 +2252,8 @@ class Enc_64199 : OpcodeHexagon {
let Inst{3-0} = Rd16{3-0};
}
class Enc_11039423 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{10-8} = Ii{9-7};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <5> Vd32;
let Inst{4-0} = Vd32{4-0};
bits <5> Rx32;
@@ -2336,9 +2287,9 @@ class Enc_13204995 : OpcodeHexagon {
let Inst{3-0} = Rt16{3-0};
}
class Enc_13338314 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{13-13} = Ii{9-9};
- let Inst{10-8} = Ii{8-6};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <5> Rt32;
@@ -2370,8 +2321,8 @@ class Enc_15380240 : OpcodeHexagon {
let Inst{12-8} = Vy32{4-0};
}
class Enc_3296020 : OpcodeHexagon {
- bits <9> Ii;
- let Inst{10-8} = Ii{8-6};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <5> Vs32;
let Inst{4-0} = Vs32{4-0};
bits <5> Rx32;
@@ -2389,17 +2340,17 @@ class Enc_2428539 : OpcodeHexagon {
let Inst{8-8} = n1{0-0};
}
class Enc_10039393 : OpcodeHexagon {
- bits <9> Ii;
- let Inst{10-8} = Ii{8-6};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <5> Vd32;
let Inst{4-0} = Vd32{4-0};
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
class Enc_9372046 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{13-13} = Ii{9-9};
- let Inst{10-8} = Ii{8-6};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <5> Rt32;
@@ -2425,16 +2376,6 @@ class Enc_16145290 : OpcodeHexagon {
bits <5> Vdd32;
let Inst{4-0} = Vdd32{4-0};
}
-class Enc_5555790 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{21-21} = Ii{9-9};
- let Inst{13-8} = Ii{8-3};
- let Inst{2-0} = Ii{2-0};
- bits <5> Vs32;
- let Inst{7-3} = Vs32{4-0};
- bits <5> Rx32;
- let Inst{20-16} = Rx32{4-0};
-}
class Enc_13783220 : OpcodeHexagon {
bits <5> Vu32;
let Inst{12-8} = Vu32{4-0};
@@ -2598,9 +2539,9 @@ class Enc_11081334 : OpcodeHexagon {
let Inst{7-3} = Vss32{4-0};
}
class Enc_9470751 : OpcodeHexagon {
- bits <11> Ii;
- let Inst{13-13} = Ii{10-10};
- let Inst{10-8} = Ii{9-7};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <5> Rt32;
@@ -3126,9 +3067,9 @@ class Enc_5023792 : OpcodeHexagon {
let Inst{4-0} = Vdd32{4-0};
}
class Enc_1244745 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{13-13} = Ii{9-9};
- let Inst{10-8} = Ii{8-6};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <5> Rt32;
let Inst{20-16} = Rt32{4-0};
bits <5> Vd32;
@@ -3162,9 +3103,9 @@ class Enc_1774350 : OpcodeHexagon {
let Inst{10-8} = Nt8{2-0};
}
class Enc_2703240 : OpcodeHexagon {
- bits <11> Ii;
- let Inst{13-13} = Ii{10-10};
- let Inst{10-8} = Ii{9-7};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <2> Qv4;
let Inst{12-11} = Qv4{1-0};
bits <5> Rt32;
@@ -3187,8 +3128,8 @@ class Enc_9789480 : OpcodeHexagon {
let Inst{7-3} = Vdd32{4-0};
}
class Enc_12244921 : OpcodeHexagon {
- bits <9> Ii;
- let Inst{10-8} = Ii{8-6};
+ bits <6> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <3> Os8;
let Inst{2-0} = Os8{2-0};
bits <5> Rx32;
@@ -3508,13 +3449,6 @@ class Enc_11065510 : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
-class Enc_8829170 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{13-13} = Ii{9-9};
- let Inst{10-8} = Ii{8-6};
- bits <5> Rt32;
- let Inst{20-16} = Rt32{4-0};
-}
class Enc_6673186 : OpcodeHexagon {
bits <13> Ii;
let Inst{26-25} = Ii{12-11};
@@ -3669,9 +3603,9 @@ class Enc_15946706 : OpcodeHexagon {
let Inst{2-0} = Rdd8{2-0};
}
class Enc_6923828 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{13-13} = Ii{9-9};
- let Inst{10-8} = Ii{8-6};
+ bits <4> Ii;
+ let Inst{13-13} = Ii{3-3};
+ let Inst{10-8} = Ii{2-0};
bits <5> Rt32;
let Inst{20-16} = Rt32{4-0};
bits <5> Vs32;
@@ -3898,8 +3832,8 @@ class Enc_7884306 : OpcodeHexagon {
let Inst{8-4} = Ii{7-3};
}
class Enc_11244923 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{10-8} = Ii{9-7};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <3> Os8;
let Inst{2-0} = Os8{2-0};
bits <5> Rx32;
@@ -3946,8 +3880,8 @@ class Enc_5915771 : OpcodeHexagon {
let Inst{8-8} = n1{0-0};
}
class Enc_14459927 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{10-8} = Ii{9-7};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <5> Vs32;
@@ -4146,8 +4080,8 @@ class Enc_11940513 : OpcodeHexagon {
let Inst{4-0} = Rt32{4-0};
}
class Enc_2735552 : OpcodeHexagon {
- bits <10> Ii;
- let Inst{10-8} = Ii{9-7};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <2> Pv4;
let Inst{12-11} = Pv4{1-0};
bits <3> Os8;
@@ -4227,8 +4161,8 @@ class Enc_14631806 : OpcodeHexagon {
let Inst{4-0} = Vdd32{4-0};
}
class Enc_12397062 : OpcodeHexagon {
- bits <9> Ii;
- let Inst{10-8} = Ii{8-6};
+ bits <3> Ii;
+ let Inst{10-8} = Ii{2-0};
bits <2> Qv4;
let Inst{12-11} = Qv4{1-0};
bits <5> Vs32;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td?rev=299664&r1=299663&r2=299664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepInstrInfo.td Thu Apr 6 12:28:21 2017
@@ -26538,7 +26538,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32Ub_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32 = vmemu($Rt32+#$Ii)",
CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_1244745, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -26554,7 +26554,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32Ub_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32 = vmemu($Rt32+#$Ii)",
CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_8437395, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -26571,7 +26571,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32Ub_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32 = vmemu($Rx32++#$Ii)",
CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_10039393, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -26588,7 +26588,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32Ub_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32 = vmemu($Rx32++#$Ii)",
CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_11039423, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -26639,7 +26639,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32 = vmem($Rt32+#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -26656,7 +26656,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32 = vmem($Rt32+#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -26674,7 +26674,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_cur_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32.cur = vmem($Rt32+#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -26690,7 +26690,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_cur_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32.cur = vmem($Rt32+#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -26707,7 +26707,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_cur_npred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b101;
@@ -26724,7 +26724,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_cur_npred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b101;
@@ -26742,7 +26742,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_cur_npred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b101;
@@ -26761,7 +26761,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_cur_npred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b101;
@@ -26818,7 +26818,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_cur_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32.cur = vmem($Rx32++#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -26835,7 +26835,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_cur_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32.cur = vmem($Rx32++#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -26886,7 +26886,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_cur_pred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b100;
@@ -26902,7 +26902,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_cur_pred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b100;
@@ -26919,7 +26919,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_cur_pred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
CVI_VM_CUR_LD, TypeCOPROC_VMEM>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b100;
@@ -26937,7 +26937,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_cur_pred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
CVI_VM_CUR_LD, TypeCOPROC_VMEM>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b100;
@@ -26991,7 +26991,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_npred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b011;
@@ -27008,7 +27008,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_npred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b011;
@@ -27026,7 +27026,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_npred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b011;
@@ -27045,7 +27045,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_npred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b011;
@@ -27102,7 +27102,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32 = vmem($Rt32+#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -27120,7 +27120,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_nt_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32 = vmem($Rt32+#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -27139,7 +27139,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_nt_cur_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32.cur = vmem($Rt32+#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -27156,7 +27156,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_nt_cur_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32.cur = vmem($Rt32+#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -27174,7 +27174,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_nt_cur_npred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b101;
@@ -27192,7 +27192,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_nt_cur_npred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b101;
@@ -27211,7 +27211,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_nt_cur_npred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b101;
@@ -27231,7 +27231,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_cur_npred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b101;
@@ -27291,7 +27291,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_cur_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32.cur = vmem($Rx32++#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -27309,7 +27309,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_cur_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32.cur = vmem($Rx32++#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -27363,7 +27363,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_cur_pred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b100;
@@ -27380,7 +27380,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_nt_cur_pred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b100;
@@ -27398,7 +27398,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_nt_cur_pred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b100;
@@ -27417,7 +27417,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_cur_pred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b100;
@@ -27474,7 +27474,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_npred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b011;
@@ -27492,7 +27492,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_nt_npred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b011;
@@ -27511,7 +27511,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_nt_npred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b011;
@@ -27531,7 +27531,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_npred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b011;
@@ -27591,7 +27591,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32 = vmem($Rx32++#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -27610,7 +27610,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32 = vmem($Rx32++#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -27667,7 +27667,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_pred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -27684,7 +27684,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_nt_pred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -27702,7 +27702,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_nt_pred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -27721,7 +27721,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_pred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -27778,7 +27778,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_tmp_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32.tmp = vmem($Rt32+#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -27795,7 +27795,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_nt_tmp_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32.tmp = vmem($Rt32+#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -27813,7 +27813,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_nt_tmp_npred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -27831,7 +27831,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_nt_tmp_npred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -27850,7 +27850,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_nt_tmp_npred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -27870,7 +27870,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_tmp_npred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -27930,7 +27930,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_tmp_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32.tmp = vmem($Rx32++#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -27948,7 +27948,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_tmp_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32.tmp = vmem($Rx32++#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -28002,7 +28002,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_tmp_pred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b110;
@@ -28019,7 +28019,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_nt_tmp_pred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b110;
@@ -28037,7 +28037,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_nt_tmp_pred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b110;
@@ -28056,7 +28056,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_nt_tmp_pred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b110;
@@ -28113,7 +28113,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32 = vmem($Rx32++#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -28131,7 +28131,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32 = vmem($Rx32++#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -28185,7 +28185,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_pred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -28201,7 +28201,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_pred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -28218,7 +28218,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_pred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -28236,7 +28236,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_pred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -28290,7 +28290,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_tmp_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32.tmp = vmem($Rt32+#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -28306,7 +28306,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_tmp_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii),
"$Vd32.tmp = vmem($Rt32+#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -28323,7 +28323,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_tmp_npred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -28340,7 +28340,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_tmp_npred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -28358,7 +28358,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_tmp_npred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -28377,7 +28377,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_tmp_npred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b111;
@@ -28434,7 +28434,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_tmp_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32.tmp = vmem($Rx32++#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -28451,7 +28451,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_tmp_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
"$Vd32.tmp = vmem($Rx32++#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b010;
@@ -28502,7 +28502,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_tmp_pred_ai : HInst<
(outs VectorRegs:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b110;
@@ -28518,7 +28518,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vL32b_tmp_pred_ai_128B : HInst<
(outs VectorRegs128B:$Vd32),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b110;
@@ -28535,7 +28535,7 @@ let isCodeGenOnly = 1;
}
def V6_vL32b_tmp_pred_pi : HInst<
(outs VectorRegs:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b110;
@@ -28553,7 +28553,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vL32b_tmp_pred_pi_128B : HInst<
(outs VectorRegs128B:$Vd32, IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> {
let Inst{7-5} = 0b110;
@@ -28607,7 +28607,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32Ub_ai : HInst<
(outs),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"vmemu($Rt32+#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b111;
@@ -28622,7 +28622,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32Ub_ai_128B : HInst<
(outs),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"vmemu($Rt32+#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b111;
@@ -28638,7 +28638,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32Ub_npred_ai : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b111;
@@ -28653,7 +28653,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32Ub_npred_ai_128B : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b111;
@@ -28669,7 +28669,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32Ub_npred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b111;
@@ -28686,7 +28686,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32Ub_npred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b111;
@@ -28737,7 +28737,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32Ub_pi : HInst<
(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"vmemu($Rx32++#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b111;
@@ -28753,7 +28753,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32Ub_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"vmemu($Rx32++#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b111;
@@ -28801,7 +28801,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32Ub_pred_ai : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b110;
@@ -28815,7 +28815,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32Ub_pred_ai_128B : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b110;
@@ -28830,7 +28830,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32Ub_pred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b110;
@@ -28846,7 +28846,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32Ub_pred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
CVI_VM_STU, TypeCVI_VM_STU>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b110;
@@ -28894,7 +28894,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_ai : HInst<
(outs),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"vmem($Rt32+#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -28910,7 +28910,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32b_ai_128B : HInst<
(outs),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"vmem($Rt32+#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -28927,7 +28927,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32b_new_ai : HInst<
(outs),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
"vmem($Rt32+#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_6608821, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b00100;
@@ -28945,7 +28945,7 @@ let opNewValue = 2;
}
def V6_vS32b_new_ai_128B : HInst<
(outs),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
"vmem($Rt32+#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2152247, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b00100;
@@ -28964,7 +28964,7 @@ let opNewValue = 2;
}
def V6_vS32b_new_npred_ai : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01101;
@@ -28982,7 +28982,7 @@ let opNewValue = 3;
}
def V6_vS32b_new_npred_ai_128B : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01101;
@@ -29001,7 +29001,7 @@ let opNewValue = 3;
}
def V6_vS32b_new_npred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01101;
@@ -29021,7 +29021,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_new_npred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01101;
@@ -29081,7 +29081,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_new_pi : HInst<
(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
"vmem($Rx32++#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_12244921, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b00100;
@@ -29100,7 +29100,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_new_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
"vmem($Rx32++#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_11244923, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b00100;
@@ -29157,7 +29157,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_new_pred_ai : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01000;
@@ -29174,7 +29174,7 @@ let opNewValue = 3;
}
def V6_vS32b_new_pred_ai_128B : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01000;
@@ -29192,7 +29192,7 @@ let opNewValue = 3;
}
def V6_vS32b_new_pred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01000;
@@ -29211,7 +29211,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_new_pred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01000;
@@ -29268,7 +29268,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_npred_ai : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b001;
@@ -29284,7 +29284,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32b_npred_ai_128B : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b001;
@@ -29301,7 +29301,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32b_npred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b001;
@@ -29319,7 +29319,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_npred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b001;
@@ -29373,7 +29373,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nqpred_ai : HInst<
(outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -29385,7 +29385,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32b_nqpred_ai_128B : HInst<
(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -29398,7 +29398,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32b_nqpred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -29412,7 +29412,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nqpred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -29454,7 +29454,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_ai : HInst<
(outs),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"vmem($Rt32+#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -29471,7 +29471,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32b_nt_ai_128B : HInst<
(outs),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"vmem($Rt32+#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -29489,7 +29489,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32b_nt_new_ai : HInst<
(outs),
-(ins IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
"vmem($Rt32+#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_6608821, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b00100;
@@ -29508,7 +29508,7 @@ let opNewValue = 2;
}
def V6_vS32b_nt_new_ai_128B : HInst<
(outs),
-(ins IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
"vmem($Rt32+#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2152247, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b00100;
@@ -29528,7 +29528,7 @@ let opNewValue = 2;
}
def V6_vS32b_nt_new_npred_ai : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01111;
@@ -29547,7 +29547,7 @@ let opNewValue = 3;
}
def V6_vS32b_nt_new_npred_ai_128B : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01111;
@@ -29567,7 +29567,7 @@ let opNewValue = 3;
}
def V6_vS32b_nt_new_npred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01111;
@@ -29588,7 +29588,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_new_npred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01111;
@@ -29651,7 +29651,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_new_pi : HInst<
(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
"vmem($Rx32++#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_12244921, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b00100;
@@ -29671,7 +29671,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_new_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
"vmem($Rx32++#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_11244923, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b00100;
@@ -29731,7 +29731,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_new_pred_ai : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8),
"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01010;
@@ -29749,7 +29749,7 @@ let opNewValue = 3;
}
def V6_vS32b_nt_new_pred_ai_128B : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8),
"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01010;
@@ -29768,7 +29768,7 @@ let opNewValue = 3;
}
def V6_vS32b_nt_new_pred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8),
"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01010;
@@ -29788,7 +29788,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_new_pred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8),
"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-3} = 0b01010;
@@ -29848,7 +29848,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_npred_ai : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b001;
@@ -29865,7 +29865,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32b_nt_npred_ai_128B : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b001;
@@ -29883,7 +29883,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32b_nt_npred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b001;
@@ -29902,7 +29902,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_npred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b001;
@@ -29959,7 +29959,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_nqpred_ai : HInst<
(outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -29972,7 +29972,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32b_nt_nqpred_ai_128B : HInst<
(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -29986,7 +29986,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32b_nt_nqpred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -30001,7 +30001,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_nqpred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b001;
@@ -30046,7 +30046,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_pi : HInst<
(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"vmem($Rx32++#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -30064,7 +30064,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"vmem($Rx32++#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -30118,7 +30118,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_pred_ai : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -30134,7 +30134,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32b_nt_pred_ai_128B : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -30151,7 +30151,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32b_nt_pred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -30169,7 +30169,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_pred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -30223,7 +30223,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_qpred_ai : HInst<
(outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -30236,7 +30236,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32b_nt_qpred_ai_128B : HInst<
(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -30250,7 +30250,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32b_nt_qpred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -30265,7 +30265,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_nt_qpred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -30310,7 +30310,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_pi : HInst<
(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"vmem($Rx32++#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -30327,7 +30327,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"vmem($Rx32++#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -30376,7 +30376,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_pred_ai : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -30391,7 +30391,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32b_pred_ai_128B : HInst<
(outs),
-(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel {
let Inst{7-5} = 0b000;
@@ -30407,7 +30407,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32b_pred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -30424,7 +30424,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_pred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -30473,7 +30473,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_qpred_ai : HInst<
(outs),
-(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32),
+(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32),
"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -30485,7 +30485,7 @@ let DecoderNamespace = "EXT_mmvec";
}
def V6_vS32b_qpred_ai_128B : HInst<
(outs),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32),
"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -30498,7 +30498,7 @@ let isCodeGenOnly = 1;
}
def V6_vS32b_qpred_pi : HInst<
(outs IntRegs:$Rx32),
-(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32),
+(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32),
"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
@@ -30512,7 +30512,7 @@ let Constraints = "$Rx32 = $Rx32in";
}
def V6_vS32b_qpred_pi_128B : HInst<
(outs IntRegs:$Rx32),
-(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32),
+(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32),
"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> {
let Inst{7-5} = 0b000;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td?rev=299664&r1=299663&r2=299664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td Thu Apr 6 12:28:21 2017
@@ -7,6 +7,9 @@
//
//===----------------------------------------------------------------------===//
+def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; }
+def s3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 0>(N->getSExtValue());}]>;
def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; }
def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; }
def s4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
@@ -70,9 +73,6 @@ def s6_0ImmPred : PatLeaf<(i32 imm), [{
def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; }
def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
def u5_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>;
-def s4_7ImmOperand : AsmOperandClass { let Name = "s4_7Imm"; }
-def s4_7Imm : Operand<i32> { let ParserMatchClass = s4_7ImmOperand; let DecoderMethod = "s4_7ImmDecoder"; let PrintMethod = "prints4_7ImmOperand"; }
-def s4_7ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 7>(N->getSExtValue());}]>;
def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; }
def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; }
def s32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
@@ -82,9 +82,6 @@ def s6_3ImmPred : PatLeaf<(i32 imm), [{
def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; }
def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
def u10_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>;
-def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; }
-def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand; let DecoderMethod = "s3_6ImmDecoder"; let PrintMethod = "prints3_6ImmOperand"; }
-def s3_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 6>(N->getSExtValue());}]>;
def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; }
def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
def u31_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>;
@@ -127,15 +124,9 @@ def b30_2ImmPred : PatLeaf<(i32 imm), [{
def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; }
def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
def u8_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>;
-def s3_7ImmOperand : AsmOperandClass { let Name = "s3_7Imm"; }
-def s3_7Imm : Operand<i32> { let ParserMatchClass = s3_7ImmOperand; let DecoderMethod = "s3_7ImmDecoder"; let PrintMethod = "prints3_7ImmOperand"; }
-def s3_7ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 7>(N->getSExtValue());}]>;
def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; }
def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
def u30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>;
-def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; }
-def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand; let DecoderMethod = "s4_6ImmDecoder"; let PrintMethod = "prints4_6ImmOperand"; }
-def s4_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 6>(N->getSExtValue());}]>;
def s10_0ImmOperand : AsmOperandClass { let Name = "s10_0Imm"; let RenderMethod = "addSignedImmOperands"; }
def s10_0Imm : Operand<i32> { let ParserMatchClass = s10_0ImmOperand; let DecoderMethod = "s10_0ImmDecoder"; }
def s10_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<10, 0>(N->getSExtValue());}]>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=299664&r1=299663&r2=299664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Thu Apr 6 12:28:21 2017
@@ -17,6 +17,16 @@ def HiReg: OutPatFrag<(ops node:$Rs), (E
def IsOrAdd: PatFrag<(ops node:$Addr, node:$off),
(or node:$Addr, node:$off), [{ return isOrEquivalentToAdd(N); }]>;
+def Iss4_6 : PatLeaf<(i32 imm), [{
+ int32_t V = N->getSExtValue();
+ return isShiftedInt<4,6>(V);
+}]>;
+
+def Iss4_7 : PatLeaf<(i32 imm), [{
+ int32_t V = N->getSExtValue();
+ return isShiftedInt<4,7>(V);
+}]>;
+
def IsPow2_32 : PatLeaf<(i32 imm), [{
uint32_t V = N->getZExtValue();
return isPowerOf2_32(V);
@@ -2746,25 +2756,25 @@ multiclass vS32b_ai_pats <ValueType VTSg
// Fold Add R+OFF into vector store.
let AddedComplexity = 10 in {
def : Pat<(alignedstore (VTSgl VectorRegs:$src1),
- (add IntRegs:$src2, s4_6ImmPred:$offset)),
- (V6_vS32b_ai IntRegs:$src2, s4_6ImmPred:$offset,
+ (add IntRegs:$src2, Iss4_6:$offset)),
+ (V6_vS32b_ai IntRegs:$src2, Iss4_6:$offset,
(VTSgl VectorRegs:$src1))>,
Requires<[UseHVXSgl]>;
def : Pat<(unalignedstore (VTSgl VectorRegs:$src1),
- (add IntRegs:$src2, s4_6ImmPred:$offset)),
- (V6_vS32Ub_ai IntRegs:$src2, s4_6ImmPred:$offset,
+ (add IntRegs:$src2, Iss4_6:$offset)),
+ (V6_vS32Ub_ai IntRegs:$src2, Iss4_6:$offset,
(VTSgl VectorRegs:$src1))>,
Requires<[UseHVXSgl]>;
// Fold Add R+OFF into vector store 128B.
def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1),
- (add IntRegs:$src2, s4_7ImmPred:$offset)),
- (V6_vS32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset,
+ (add IntRegs:$src2, Iss4_7:$offset)),
+ (V6_vS32b_ai_128B IntRegs:$src2, Iss4_7:$offset,
(VTDbl VectorRegs128B:$src1))>,
Requires<[UseHVXDbl]>;
def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1),
- (add IntRegs:$src2, s4_7ImmPred:$offset)),
- (V6_vS32Ub_ai_128B IntRegs:$src2, s4_7ImmPred:$offset,
+ (add IntRegs:$src2, Iss4_7:$offset)),
+ (V6_vS32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset,
(VTDbl VectorRegs128B:$src1))>,
Requires<[UseHVXDbl]>;
}
@@ -2795,18 +2805,18 @@ multiclass vL32b_ai_pats <ValueType VTSg
// Fold Add R+OFF into vector load.
let AddedComplexity = 10 in {
- def : Pat<(VTDbl (alignedload (add IntRegs:$src2, s4_7ImmPred:$offset))),
- (V6_vL32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>,
+ def : Pat<(VTDbl (alignedload (add IntRegs:$src2, Iss4_7:$offset))),
+ (V6_vL32b_ai_128B IntRegs:$src2, Iss4_7:$offset)>,
Requires<[UseHVXDbl]>;
- def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, s4_7ImmPred:$offset))),
- (V6_vL32Ub_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>,
+ def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, Iss4_7:$offset))),
+ (V6_vL32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset)>,
Requires<[UseHVXDbl]>;
- def : Pat<(VTSgl (alignedload (add IntRegs:$src2, s4_6ImmPred:$offset))),
- (V6_vL32b_ai IntRegs:$src2, s4_6ImmPred:$offset)>,
+ def : Pat<(VTSgl (alignedload (add IntRegs:$src2, Iss4_6:$offset))),
+ (V6_vL32b_ai IntRegs:$src2, Iss4_6:$offset)>,
Requires<[UseHVXSgl]>;
- def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, s4_6ImmPred:$offset))),
- (V6_vL32Ub_ai IntRegs:$src2, s4_6ImmPred:$offset)>,
+ def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, Iss4_6:$offset))),
+ (V6_vL32Ub_ai IntRegs:$src2, Iss4_6:$offset)>,
Requires<[UseHVXSgl]>;
}
}
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp?rev=299664&r1=299663&r2=299664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp Thu Apr 6 12:28:21 2017
@@ -125,46 +125,6 @@ void HexagonInstPrinter::printNOneImmOpe
O << -1;
}
-void HexagonInstPrinter::prints3_6ImmOperand(MCInst const *MI, unsigned OpNo,
- raw_ostream &O) const {
- int64_t Imm;
- bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
- Imm = SignExtend64<9>(Imm);
- assert(Success); (void)Success;
- assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");
- O << formatImm(Imm/64);
-}
-
-void HexagonInstPrinter::prints3_7ImmOperand(MCInst const *MI, unsigned OpNo,
- raw_ostream &O) const {
- int64_t Imm;
- bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
- Imm = SignExtend64<10>(Imm);
- assert(Success); (void)Success;
- assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO.");
- O << formatImm(Imm/128);
-}
-
-void HexagonInstPrinter::prints4_6ImmOperand(MCInst const *MI, unsigned OpNo,
- raw_ostream &O) const {
- int64_t Imm;
- bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
- Imm = SignExtend64<10>(Imm);
- assert(Success); (void)Success;
- assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");
- O << formatImm(Imm/64);
-}
-
-void HexagonInstPrinter::prints4_7ImmOperand(MCInst const *MI, unsigned OpNo,
- raw_ostream &O) const {
- int64_t Imm;
- bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
- Imm = SignExtend64<11>(Imm);
- assert(Success); (void)Success;
- assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO.");
- O << formatImm(Imm/128);
-}
-
void HexagonInstPrinter::printGlobalOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const {
printOperand(MI, OpNo, O);
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h?rev=299664&r1=299663&r2=299664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h Thu Apr 6 12:28:21 2017
@@ -44,14 +44,6 @@ public:
raw_ostream &O) const;
void printNOneImmOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const;
- void prints3_6ImmOperand(MCInst const *MI, unsigned OpNo,
- raw_ostream &O) const;
- void prints3_7ImmOperand(MCInst const *MI, unsigned OpNo,
- raw_ostream &O) const;
- void prints4_6ImmOperand(MCInst const *MI, unsigned OpNo,
- raw_ostream &O) const;
- void prints4_7ImmOperand(MCInst const *MI, unsigned OpNo,
- raw_ostream &O) const;
void printBranchOperand(MCInst const *MI, unsigned OpNo,
raw_ostream &O) const;
void printCallOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const;
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