[PATCH] D31714: [X86] Added missing mayLoad/mayStore attributes to some X86 instructions

[Ayman Musa via Phabricator via llvm-commits]

aymanmus added a comment.

@craig.topper - Yes, all X86 instructions that have both register and memory forms and can be legally folded will be included in the generated tables.



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Comment at: lib/Target/X86/X86InstrVMX.td:51
+let mayStore = 1 in {
+def VMREAD64rm : I<0x78, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
+  "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
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craig.topper wrote:
> Do you mind changing the name of these to VMREAD64mr and VMREAD32mr as a NFC pre-patch. That would be more consistent with our other instruction names.
Done. (https://reviews.llvm.org/D31743)


https://reviews.llvm.org/D31714