[PATCH] D31161: [AMDGPU] New Waitcnt Insertion Pass

[Kannan Narayanan via Phabricator via llvm-commits]

kanarayan updated this revision to Diff 94310.
kanarayan marked 19 inline comments as done.
kanarayan added a comment.

The update includes the following after rebasing:

Re-organize the getRegInterval as follows:

1. Support the registers covered under isSGPRReg that are allocatable.
2. Assert that the register numbers are within bounds.

Check the GDS bit and avoid the loop on the memory operands. For DS operations, additionally check they are either load or a store.

Fix the LGKM bit for ds_bpermute, ds_permute operations that do not access DS.

Add comments on TODO items to the code. The following are some of the other items:

1. We currently list all !VGPR registers under isSGPRReg that causes confusion.
2. There are waintcnt flags/bits which do not appear to be consistently set (example: ds_swizzle). I need to verify the flag bits are set property and then could use the bits in the new pass.


https://reviews.llvm.org/D31161

Files:
  lib/Target/AMDGPU/AMDGPU.h
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/CMakeLists.txt
  lib/Target/AMDGPU/DSInstructions.td
  lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  test/CodeGen/AMDGPU/basic-branch.ll
  test/CodeGen/AMDGPU/branch-condition-and.ll
  test/CodeGen/AMDGPU/branch-relaxation.ll
  test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  test/CodeGen/AMDGPU/indirect-addressing-si.ll
  test/CodeGen/AMDGPU/infinite-loop.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.image.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
  test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
  test/CodeGen/AMDGPU/ret_jump.ll
  test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
  test/CodeGen/AMDGPU/smrd-vccz-bug.ll
  test/CodeGen/AMDGPU/spill-m0.ll
  test/CodeGen/AMDGPU/valu-i1.ll

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