[PATCH] D31609: [SystemZ] Prevent Merging Bitcast with non-normal loads
Nirav Dave via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 5 08:55:29 PDT 2017
This revision was automatically updated to reflect the committed changes.
Closed by commit rL299552: [SystemZ] Prevent Merging Bitcast with non-normal loads (authored by niravd).
Changed prior to commit:
https://reviews.llvm.org/D31609?vs=94231&id=94238#toc
Repository:
rL LLVM
https://reviews.llvm.org/D31609
Files:
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/trunk/test/CodeGen/SystemZ/pr32505.ll
Index: llvm/trunk/test/CodeGen/SystemZ/pr32505.ll
===================================================================
--- llvm/trunk/test/CodeGen/SystemZ/pr32505.ll
+++ llvm/trunk/test/CodeGen/SystemZ/pr32505.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=zEC12 -o - %s | FileCheck %s
+
+target triple = "s390x-ibm-linux"
+
+define <2 x float> @pr32505(<2 x i8> * %a) {
+; CHECK-LABEL: pr32505:
+; CHECK: # BB#0:
+; CHECK-NEXT: lbh %r0, 0(%r2)
+; CHECK-NEXT: ldgr %f0, %r0
+; CHECK-NEXT: lbh %r0, 1(%r2)
+; CHECK-NEXT: ldgr %f2, %r0
+; CHECK-NEXT: # kill: %F0S<def> %F0S<kill> %F0D<kill>
+; CHECK-NEXT: # kill: %F2S<def> %F2S<kill> %F2D<kill>
+; CHECK-NEXT: br %r14
+ %L17 = load <2 x i8>, <2 x i8>* %a
+ %Se21 = sext <2 x i8> %L17 to <2 x i32>
+ %BC = bitcast <2 x i32> %Se21 to <2 x float>
+ ret <2 x float> %BC
+}
Index: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -2792,8 +2792,9 @@
// but we need this case for bitcasts that are created during lowering
// and which are then lowered themselves.
if (auto *LoadN = dyn_cast<LoadSDNode>(In))
- return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(),
- LoadN->getMemOperand());
+ if (ISD::isNormalLoad(LoadN))
+ return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(),
+ LoadN->getMemOperand());
if (InVT == MVT::i32 && ResVT == MVT::f32) {
SDValue In64;
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