[llvm] r299552 - [SystemZ] Prevent Merging Bitcast with non-normal loads

Nirav Dave via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 5 08:42:48 PDT 2017


Author: niravd
Date: Wed Apr  5 10:42:48 2017
New Revision: 299552

URL: http://llvm.org/viewvc/llvm-project?rev=299552&view=rev
Log:
[SystemZ] Prevent Merging Bitcast with non-normal loads

Fixes PR32505.

Reviewers: uweigand, jonpa

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31609

Added:
    llvm/trunk/test/CodeGen/SystemZ/pr32505.ll
Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=299552&r1=299551&r2=299552&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Wed Apr  5 10:42:48 2017
@@ -2792,8 +2792,9 @@ SDValue SystemZTargetLowering::lowerBITC
   // but we need this case for bitcasts that are created during lowering
   // and which are then lowered themselves.
   if (auto *LoadN = dyn_cast<LoadSDNode>(In))
-    return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(),
-                       LoadN->getMemOperand());
+    if (ISD::isNormalLoad(LoadN))
+      return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(),
+                         LoadN->getMemOperand());
 
   if (InVT == MVT::i32 && ResVT == MVT::f32) {
     SDValue In64;

Added: llvm/trunk/test/CodeGen/SystemZ/pr32505.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/pr32505.ll?rev=299552&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/pr32505.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/pr32505.ll Wed Apr  5 10:42:48 2017
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=zEC12 -o - %s | FileCheck %s
+
+target triple = "s390x-ibm-linux"
+
+define <2 x float> @pr32505(<2 x i8> * %a) {
+; CHECK-LABEL: pr32505:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    lbh %r0, 0(%r2)
+; CHECK-NEXT:    ldgr %f0, %r0
+; CHECK-NEXT:    lbh %r0, 1(%r2)
+; CHECK-NEXT:    ldgr %f2, %r0
+; CHECK-NEXT:    # kill: %F0S<def> %F0S<kill> %F0D<kill>
+; CHECK-NEXT:    # kill: %F2S<def> %F2S<kill> %F2D<kill>
+; CHECK-NEXT:    br %r14
+  %L17 = load <2 x i8>, <2 x i8>* %a
+  %Se21 = sext <2 x i8> %L17 to <2 x i32>
+  %BC = bitcast <2 x i32> %Se21 to <2 x float>
+  ret <2 x float> %BC
+}




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