[llvm] r299529 - Add MCContext argument to MCAsmBackend::applyFixup for error reporting

Alexander Kornienko via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 5 05:03:29 PDT 2017


Fixed the breakage in r299535. No need to revert.

On Wed, Apr 5, 2017 at 1:59 PM, Alexander Kornienko <alexfh at google.com>
wrote:

> On a side note: it doesn't seem like any buildbots detected this. Are
> there no buildbots covering WebAssembly?
>
> On Wed, Apr 5, 2017 at 1:34 PM, Alexander Kornienko <alexfh at google.com>
> wrote:
>
>> FYI, this patch breaks our build:
>>
>> lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp:41:55:
>> error: non-virtual member function marked 'override' hides virtual member
>> function
>>                   uint64_t Value, bool IsPCRel) const override;
>>                                                       ^
>>
>> Please fix or revert.
>>
>> On Wed, Apr 5, 2017 at 12:16 PM, Alex Bradbury via llvm-commits <
>> llvm-commits at lists.llvm.org> wrote:
>>
>>> Author: asb
>>> Date: Wed Apr  5 05:16:14 2017
>>> New Revision: 299529
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=299529&view=rev
>>> Log:
>>> Add MCContext argument to MCAsmBackend::applyFixup for error reporting
>>>
>>> A number of backends (AArch64, MIPS, ARM) have been using
>>> MCContext::reportError to report issues such as out-of-range fixup
>>> values in
>>> their TgtAsmBackend. This is great, but because MCContext couldn't
>>> easily be
>>> threaded through to the adjustFixupValue helper function from its usual
>>> callsite (applyFixup), these backends ended up adding an MCContext*
>>> argument
>>> and adding another call to applyFixup to processFixupValue. Adding an
>>> MCContext parameter to applyFixup makes this unnecessary, and even
>>> better -
>>> applyFixup can take a reference to MCContext rather than a potentially
>>> null
>>> pointer.
>>>
>>> Differential Revision: https://reviews.llvm.org/D30264
>>>
>>> Modified:
>>>     llvm/trunk/include/llvm/MC/MCAsmBackend.h
>>>     llvm/trunk/lib/MC/MCAssembler.cpp
>>>     llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
>>>     llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
>>>     llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
>>>     llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
>>>     llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
>>>     llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
>>>     llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
>>>     llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
>>>     llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
>>>     llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
>>>     llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
>>>     llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
>>>     llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
>>>     llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
>>>     llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
>>>     llvm/trunk/test/MC/ARM/quad-relocation.s
>>>
>>> Modified: llvm/trunk/include/llvm/MC/MCAsmBackend.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/
>>> MC/MCAsmBackend.h?rev=299529&r1=299528&r2=299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/include/llvm/MC/MCAsmBackend.h (original)
>>> +++ llvm/trunk/include/llvm/MC/MCAsmBackend.h Wed Apr  5 05:16:14 2017
>>> @@ -71,9 +71,11 @@ public:
>>>
>>>    /// Apply the \p Value for given \p Fixup into the provided data
>>> fragment, at
>>>    /// the offset specified by the fixup and following the fixup kind as
>>> -  /// appropriate.
>>> +  /// appropriate. Errors (such as an out of range fixup value) should
>>> be
>>> +  /// reported via \p Ctx.
>>>    virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned
>>> DataSize,
>>> -                          uint64_t Value, bool IsPCRel) const = 0;
>>> +                          uint64_t Value, bool IsPCRel,
>>> +                          MCContext &Ctx) const = 0;
>>>
>>>    /// @}
>>>
>>>
>>> Modified: llvm/trunk/lib/MC/MCAssembler.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsse
>>> mbler.cpp?rev=299529&r1=299528&r2=299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/MC/MCAssembler.cpp (original)
>>> +++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Apr  5 05:16:14 2017
>>> @@ -732,8 +732,8 @@ void MCAssembler::layout(MCAsmLayout &La
>>>          uint64_t FixedValue;
>>>          bool IsPCRel;
>>>          std::tie(FixedValue, IsPCRel) = handleFixup(Layout, Frag,
>>> Fixup);
>>> -        getBackend().applyFixup(Fixup, Contents.data(),
>>> -                                Contents.size(), FixedValue, IsPCRel);
>>> +        getBackend().applyFixup(Fixup, Contents.data(), Contents.size(),
>>> +                                FixedValue, IsPCRel, getContext());
>>>        }
>>>      }
>>>    }
>>>
>>> Modified: llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend
>>> .cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AA
>>> rch64/MCTargetDesc/AArch64AsmBackend.cpp?rev=299529&r1=29952
>>> 8&r2=299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
>>> Wed Apr  5 05:16:14 2017
>>> @@ -73,7 +73,7 @@ public:
>>>    }
>>>
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t Value, bool IsPCRel) const override;
>>> +                  uint64_t Value, bool IsPCRel, MCContext &Ctx) const
>>> override;
>>>
>>>    bool mayNeedRelaxation(const MCInst &Inst) const override;
>>>    bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
>>> @@ -138,15 +138,15 @@ static unsigned AdrImmBits(unsigned Valu
>>>  }
>>>
>>>  static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
>>> -                                 MCContext *Ctx) {
>>> +                                 MCContext &Ctx) {
>>>    unsigned Kind = Fixup.getKind();
>>>    int64_t SignedValue = static_cast<int64_t>(Value);
>>>    switch (Kind) {
>>>    default:
>>>      llvm_unreachable("Unknown fixup kind!");
>>>    case AArch64::fixup_aarch64_pcrel_adr_imm21:
>>> -    if (Ctx && (SignedValue > 2097151 || SignedValue < -2097152))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
>>> +    if (SignedValue > 2097151 || SignedValue < -2097152)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
>>>      return AdrImmBits(Value & 0x1fffffULL);
>>>    case AArch64::fixup_aarch64_pcrel_adrp_imm21:
>>>      return AdrImmBits((Value & 0x1fffff000ULL) >> 12);
>>> @@ -154,66 +154,65 @@ static uint64_t adjustFixupValue(const M
>>>    case AArch64::fixup_aarch64_pcrel_branch19:
>>>      // Signed 21-bit immediate
>>>      if (SignedValue > 2097151 || SignedValue < -2097152)
>>> -      if (Ctx) Ctx->reportError(Fixup.getLoc(), "fixup value out of
>>> range");
>>> -    if (Ctx && (Value & 0x3))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup not sufficiently
>>> aligned");
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
>>> +    if (Value & 0x3)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently
>>> aligned");
>>>      // Low two bits are not encoded.
>>>      return (Value >> 2) & 0x7ffff;
>>>    case AArch64::fixup_aarch64_add_imm12:
>>>    case AArch64::fixup_aarch64_ldst_imm12_scale1:
>>>      // Unsigned 12-bit immediate
>>> -    if (Ctx && Value >= 0x1000)
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
>>> +    if (Value >= 0x1000)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
>>>      return Value;
>>>    case AArch64::fixup_aarch64_ldst_imm12_scale2:
>>>      // Unsigned 12-bit immediate which gets multiplied by 2
>>> -    if (Ctx && (Value >= 0x2000))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
>>> -    if (Ctx && (Value & 0x1))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");
>>> +    if (Value >= 0x2000)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
>>> +    if (Value & 0x1)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");
>>>      return Value >> 1;
>>>    case AArch64::fixup_aarch64_ldst_imm12_scale4:
>>>      // Unsigned 12-bit immediate which gets multiplied by 4
>>> -    if (Ctx && (Value >= 0x4000))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
>>> -    if (Ctx && (Value & 0x3))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup must be 4-byte aligned");
>>> +    if (Value >= 0x4000)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
>>> +    if (Value & 0x3)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup must be 4-byte aligned");
>>>      return Value >> 2;
>>>    case AArch64::fixup_aarch64_ldst_imm12_scale8:
>>>      // Unsigned 12-bit immediate which gets multiplied by 8
>>> -    if (Ctx && (Value >= 0x8000))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
>>> -    if (Ctx && (Value & 0x7))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup must be 8-byte aligned");
>>> +    if (Value >= 0x8000)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
>>> +    if (Value & 0x7)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup must be 8-byte aligned");
>>>      return Value >> 3;
>>>    case AArch64::fixup_aarch64_ldst_imm12_scale16:
>>>      // Unsigned 12-bit immediate which gets multiplied by 16
>>> -    if (Ctx && (Value >= 0x10000))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
>>> -    if (Ctx && (Value & 0xf))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup must be 16-byte
>>> aligned");
>>> +    if (Value >= 0x10000)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
>>> +    if (Value & 0xf)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup must be 16-byte aligned");
>>>      return Value >> 4;
>>>    case AArch64::fixup_aarch64_movw:
>>> -    if (Ctx)
>>> -      Ctx->reportError(Fixup.getLoc(),
>>> -                       "no resolvable MOVZ/MOVK fixups supported yet");
>>> +    Ctx.reportError(Fixup.getLoc(),
>>> +                    "no resolvable MOVZ/MOVK fixups supported yet");
>>>      return Value;
>>>    case AArch64::fixup_aarch64_pcrel_branch14:
>>>      // Signed 16-bit immediate
>>> -    if (Ctx && (SignedValue > 32767 || SignedValue < -32768))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
>>> +    if (SignedValue > 32767 || SignedValue < -32768)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
>>>      // Low two bits are not encoded (4-byte alignment assumed).
>>> -    if (Ctx && (Value & 0x3))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup not sufficiently
>>> aligned");
>>> +    if (Value & 0x3)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently
>>> aligned");
>>>      return (Value >> 2) & 0x3fff;
>>>    case AArch64::fixup_aarch64_pcrel_branch26:
>>>    case AArch64::fixup_aarch64_pcrel_call26:
>>>      // Signed 28-bit immediate
>>> -    if (Ctx && (SignedValue > 134217727 || SignedValue < -134217728))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
>>> +    if (SignedValue > 134217727 || SignedValue < -134217728)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
>>>      // Low two bits are not encoded (4-byte alignment assumed).
>>> -    if (Ctx && (Value & 0x3))
>>> -      Ctx->reportError(Fixup.getLoc(), "fixup not sufficiently
>>> aligned");
>>> +    if (Value & 0x3)
>>> +      Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently
>>> aligned");
>>>      return (Value >> 2) & 0x3ffffff;
>>>    case FK_Data_1:
>>>    case FK_Data_2:
>>> @@ -264,13 +263,13 @@ unsigned AArch64AsmBackend::getFixupKind
>>>
>>>  void AArch64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
>>>                                     unsigned DataSize, uint64_t Value,
>>> -                                   bool IsPCRel) const {
>>> +                                   bool IsPCRel, MCContext &Ctx) const {
>>>    unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
>>>    if (!Value)
>>>      return; // Doesn't change encoding.
>>>    MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
>>>    // Apply any target-specific value adjustments.
>>> -  Value = adjustFixupValue(Fixup, Value, nullptr);
>>> +  Value = adjustFixupValue(Fixup, Value, Ctx);
>>>
>>>    // Shift the value into position.
>>>    Value <<= Info.TargetOffset;
>>> @@ -521,17 +520,6 @@ public:
>>>
>>>      return CompactUnwindEncoding;
>>>    }
>>> -
>>> -  void processFixupValue(const MCAssembler &Asm, const MCAsmLayout
>>> &Layout,
>>> -                         const MCFixup &Fixup, const MCFragment *DF,
>>> -                         const MCValue &Target, uint64_t &Value,
>>> -                         bool &IsResolved) override {
>>> -    // Try to get the encoded value for the fixup as-if we're mapping
>>> it into
>>> -    // the instruction. This allows adjustFixupValue() to issue a
>>> diagnostic
>>> -    // if the value is invalid.
>>> -    if (IsResolved)
>>> -      (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
>>> -  }
>>>  };
>>>
>>>  } // end anonymous namespace
>>> @@ -575,12 +563,6 @@ void ELFAArch64AsmBackend::processFixupV
>>>    // to the linker -- a relocation!
>>>    if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_a
>>> drp_imm21)
>>>      IsResolved = false;
>>> -
>>> -  // Try to get the encoded value for the fixup as-if we're mapping it
>>> into
>>> -  // the instruction. This allows adjustFixupValue() to issue a
>>> diagnostic
>>> -  // if the value is invalid.
>>> -  if (IsResolved)
>>> -    (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
>>>  }
>>>
>>>  }
>>>
>>> Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AM
>>> DGPU/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=299529&r1=299528&
>>> r2=299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp Wed
>>> Apr  5 05:16:14 2017
>>> @@ -37,7 +37,7 @@ public:
>>>                           bool &IsResolved) override;
>>>
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t Value, bool IsPCRel) const override;
>>> +                  uint64_t Value, bool IsPCRel, MCContext &Ctx) const
>>> override;
>>>    bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
>>>                              const MCRelaxableFragment *DF,
>>>                              const MCAsmLayout &Layout) const override {
>>> @@ -131,7 +131,7 @@ void AMDGPUAsmBackend::processFixupValue
>>>
>>>  void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
>>>                                    unsigned DataSize, uint64_t Value,
>>> -                                  bool IsPCRel) const {
>>> +                                  bool IsPCRel, MCContext &Ctx) const {
>>>    if (!Value)
>>>      return; // Doesn't change encoding.
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AR
>>> M/MCTargetDesc/ARMAsmBackend.cpp?rev=299529&r1=299528&r2=299
>>> 529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed Apr  5
>>> 05:16:14 2017
>>> @@ -357,13 +357,13 @@ static uint32_t joinHalfWords(uint32_t F
>>>  }
>>>
>>>  unsigned ARMAsmBackend::adjustFixupValue(const MCFixup &Fixup,
>>> uint64_t Value,
>>> -                                         bool IsPCRel, MCContext *Ctx,
>>> +                                         bool IsPCRel, MCContext &Ctx,
>>>                                           bool IsLittleEndian,
>>>                                           bool IsResolved) const {
>>>    unsigned Kind = Fixup.getKind();
>>>    switch (Kind) {
>>>    default:
>>> -    if (Ctx) Ctx->reportError(Fixup.getLoc(), "bad relocation fixup
>>> type");
>>> +    Ctx.reportError(Fixup.getLoc(), "bad relocation fixup type");
>>>      return 0;
>>>    case FK_Data_1:
>>>    case FK_Data_2:
>>> @@ -413,8 +413,8 @@ unsigned ARMAsmBackend::adjustFixupValue
>>>        Value = -Value;
>>>        isAdd = false;
>>>      }
>>> -    if (Ctx && Value >= 4096) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>> +    if (Value >= 4096) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>>        return 0;
>>>      }
>>>      Value |= isAdd << 23;
>>> @@ -434,8 +434,8 @@ unsigned ARMAsmBackend::adjustFixupValue
>>>        Value = -Value;
>>>        opc = 2; // 0b0010
>>>      }
>>> -    if (Ctx && ARM_AM::getSOImmVal(Value) == -1) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>> +    if (ARM_AM::getSOImmVal(Value) == -1) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>>        return 0;
>>>      }
>>>      // Encode the immediate and shift the opcode into place.
>>> @@ -542,8 +542,8 @@ unsigned ARMAsmBackend::adjustFixupValue
>>>      //
>>>      // Note that the halfwords are stored high first, low second; so we
>>> need
>>>      // to transpose the fixup value here to map properly.
>>> -    if (Ctx && Value % 4 != 0) {
>>> -      Ctx->reportError(Fixup.getLoc(), "misaligned ARM call
>>> destination");
>>> +    if (Value % 4 != 0) {
>>> +      Ctx.reportError(Fixup.getLoc(), "misaligned ARM call
>>> destination");
>>>        return 0;
>>>      }
>>>
>>> @@ -569,10 +569,10 @@ unsigned ARMAsmBackend::adjustFixupValue
>>>    case ARM::fixup_arm_thumb_cp:
>>>      // On CPUs supporting Thumb2, this will be relaxed to an ldr.w,
>>> otherwise we
>>>      // could have an error on our hands.
>>> -    if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] &&
>>> IsResolved) {
>>> +    if (!STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) {
>>>        const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup,
>>> Value);
>>>        if (FixupDiagnostic) {
>>> -        Ctx->reportError(Fixup.getLoc(), FixupDiagnostic);
>>> +        Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
>>>          return 0;
>>>        }
>>>      }
>>> @@ -582,8 +582,8 @@ unsigned ARMAsmBackend::adjustFixupValue
>>>      // CB instructions can only branch to offsets in [4, 126] in
>>> multiples of 2
>>>      // so ensure that the raw value LSB is zero and it lies in [2, 130].
>>>      // An offset of 2 will be relaxed to a NOP.
>>> -    if (Ctx && ((int64_t)Value < 2 || Value > 0x82 || Value & 1)) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>> +    if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>>        return 0;
>>>      }
>>>      // Offset by 4 and don't encode the lower bit, which is always 0.
>>> @@ -593,21 +593,21 @@ unsigned ARMAsmBackend::adjustFixupValue
>>>    }
>>>    case ARM::fixup_arm_thumb_br:
>>>      // Offset by 4 and don't encode the lower bit, which is always 0.
>>> -    if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] &&
>>> -               !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) {
>>> +    if (!STI->getFeatureBits()[ARM::FeatureThumb2] &&
>>> +        !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) {
>>>        const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup,
>>> Value);
>>>        if (FixupDiagnostic) {
>>> -        Ctx->reportError(Fixup.getLoc(), FixupDiagnostic);
>>> +        Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
>>>          return 0;
>>>        }
>>>      }
>>>      return ((Value - 4) >> 1) & 0x7ff;
>>>    case ARM::fixup_arm_thumb_bcc:
>>>      // Offset by 4 and don't encode the lower bit, which is always 0.
>>> -    if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2]) {
>>> +    if (!STI->getFeatureBits()[ARM::FeatureThumb2]) {
>>>        const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup,
>>> Value);
>>>        if (FixupDiagnostic) {
>>> -        Ctx->reportError(Fixup.getLoc(), FixupDiagnostic);
>>> +        Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
>>>          return 0;
>>>        }
>>>      }
>>> @@ -621,8 +621,8 @@ unsigned ARMAsmBackend::adjustFixupValue
>>>        isAdd = false;
>>>      }
>>>      // The value has the low 4 bits encoded in [3:0] and the high 4 in
>>> [11:8].
>>> -    if (Ctx && Value >= 256) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>> +    if (Value >= 256) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>>        return 0;
>>>      }
>>>      Value = (Value & 0xf) | ((Value & 0xf0) << 4);
>>> @@ -642,8 +642,8 @@ unsigned ARMAsmBackend::adjustFixupValue
>>>      }
>>>      // These values don't encode the low two bits since they're always
>>> zero.
>>>      Value >>= 2;
>>> -    if (Ctx && Value >= 256) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>> +    if (Value >= 256) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>>        return 0;
>>>      }
>>>      Value |= isAdd << 23;
>>> @@ -668,13 +668,13 @@ unsigned ARMAsmBackend::adjustFixupValue
>>>        isAdd = false;
>>>      }
>>>      // These values don't encode the low bit since it's always zero.
>>> -    if (Ctx && (Value & 1)) {
>>> -      Ctx->reportError(Fixup.getLoc(), "invalid value for this fixup");
>>> +    if (Value & 1) {
>>> +      Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup");
>>>        return 0;
>>>      }
>>>      Value >>= 1;
>>> -    if (Ctx && Value >= 256) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>> +    if (Value >= 256) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup
>>> value");
>>>        return 0;
>>>      }
>>>      Value |= isAdd << 23;
>>> @@ -688,8 +688,8 @@ unsigned ARMAsmBackend::adjustFixupValue
>>>    }
>>>    case ARM::fixup_arm_mod_imm:
>>>      Value = ARM_AM::getSOImmVal(Value);
>>> -    if (Ctx && Value >> 12) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range immediate fixup
>>> value");
>>> +    if (Value >> 12) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup
>>> value");
>>>        return 0;
>>>      }
>>>      return Value;
>>> @@ -738,12 +738,6 @@ void ARMAsmBackend::processFixupValue(co
>>>              (unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||
>>>              (unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))
>>>      IsResolved = false;
>>> -
>>> -  // Try to get the encoded value for the fixup as-if we're mapping it
>>> into
>>> -  // the instruction. This allows adjustFixupValue() to issue a
>>> diagnostic
>>> -  // if the value is invalid.
>>> -  (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(),
>>> -                         IsLittleEndian, IsResolved);
>>>  }
>>>
>>>  /// getFixupKindNumBytes - The number of bytes the fixup may change.
>>> @@ -847,11 +841,10 @@ static unsigned getFixupKindContainerSiz
>>>  }
>>>
>>>  void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
>>> -                               unsigned DataSize, uint64_t Value,
>>> -                               bool IsPCRel) const {
>>> +                               unsigned DataSize, uint64_t Value, bool
>>> IsPCRel,
>>> +                               MCContext &Ctx) const {
>>>    unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
>>> -  Value =
>>> -      adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian,
>>> true);
>>> +  Value = adjustFixupValue(Fixup, Value, IsPCRel, Ctx, IsLittleEndian,
>>> true);
>>>    if (!Value)
>>>      return; // Doesn't change encoding.
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AR
>>> M/MCTargetDesc/ARMAsmBackend.h?rev=299529&r1=299528&r2=299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h (original)
>>> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h Wed Apr  5
>>> 05:16:14 2017
>>> @@ -46,11 +46,11 @@ public:
>>>                           bool &IsResolved) override;
>>>
>>>    unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, bool
>>> IsPCRel,
>>> -                            MCContext *Ctx, bool IsLittleEndian,
>>> +                            MCContext &Ctx, bool IsLittleEndian,
>>>                              bool IsResolved) const;
>>>
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t Value, bool IsPCRel) const override;
>>> +                  uint64_t Value, bool IsPCRel, MCContext &Ctx) const
>>> override;
>>>
>>>    unsigned getRelaxedOpcode(unsigned Op) const;
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AR
>>> M/MCTargetDesc/ARMELFObjectWriter.cpp?rev=299529&r1=299528&r
>>> 2=299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Wed
>>> Apr  5 05:16:14 2017
>>> @@ -9,6 +9,7 @@
>>>
>>>  #include "MCTargetDesc/ARMFixupKinds.h"
>>>  #include "MCTargetDesc/ARMMCTargetDesc.h"
>>> +#include "llvm/MC/MCContext.h"
>>>  #include "llvm/MC/MCELFObjectWriter.h"
>>>  #include "llvm/MC/MCExpr.h"
>>>  #include "llvm/MC/MCFixup.h"
>>> @@ -25,9 +26,8 @@ namespace {
>>>    class ARMELFObjectWriter : public MCELFObjectTargetWriter {
>>>      enum { DefaultEABIVersion = 0x05000000U };
>>>
>>> -    unsigned GetRelocTypeInner(const MCValue &Target,
>>> -                               const MCFixup &Fixup,
>>> -                               bool IsPCRel) const;
>>> +    unsigned GetRelocTypeInner(const MCValue &Target, const MCFixup
>>> &Fixup,
>>> +                               bool IsPCRel, MCContext &Ctx) const;
>>>
>>>    public:
>>>      ARMELFObjectWriter(uint8_t OSABI);
>>> @@ -69,19 +69,20 @@ bool ARMELFObjectWriter::needsRelocateWi
>>>  unsigned ARMELFObjectWriter::getRelocType(MCContext &Ctx, const
>>> MCValue &Target,
>>>                                            const MCFixup &Fixup,
>>>                                            bool IsPCRel) const {
>>> -  return GetRelocTypeInner(Target, Fixup, IsPCRel);
>>> +  return GetRelocTypeInner(Target, Fixup, IsPCRel, Ctx);
>>>  }
>>>
>>>  unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
>>>                                                 const MCFixup &Fixup,
>>> -                                               bool IsPCRel) const  {
>>> +                                               bool IsPCRel,
>>> +                                               MCContext &Ctx) const {
>>>    MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
>>>
>>>    unsigned Type = 0;
>>>    if (IsPCRel) {
>>>      switch ((unsigned)Fixup.getKind()) {
>>>      default:
>>> -      report_fatal_error("unsupported relocation on symbol");
>>> +      Ctx.reportFatalError(Fixup.getLoc(), "unsupported relocation on
>>> symbol");
>>>        return ELF::R_ARM_NONE;
>>>      case FK_Data_4:
>>>        switch (Modifier) {
>>> @@ -160,7 +161,7 @@ unsigned ARMELFObjectWriter::GetRelocTyp
>>>    } else {
>>>      switch ((unsigned)Fixup.getKind()) {
>>>      default:
>>> -      report_fatal_error("unsupported relocation on symbol");
>>> +      Ctx.reportFatalError(Fixup.getLoc(), "unsupported relocation on
>>> symbol");
>>>        return ELF::R_ARM_NONE;
>>>      case FK_Data_1:
>>>        switch (Modifier) {
>>>
>>> Modified: llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BP
>>> F/MCTargetDesc/BPFAsmBackend.cpp?rev=299529&r1=299528&r2=299
>>> 529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp (original)
>>> +++ llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp Wed Apr  5
>>> 05:16:14 2017
>>> @@ -28,7 +28,7 @@ public:
>>>    ~BPFAsmBackend() override = default;
>>>
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t Value, bool IsPCRel) const override;
>>> +                  uint64_t Value, bool IsPCRel, MCContext &Ctx) const
>>> override;
>>>
>>>    MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const
>>> override;
>>>
>>> @@ -62,8 +62,8 @@ bool BPFAsmBackend::writeNopData(uint64_
>>>  }
>>>
>>>  void BPFAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
>>> -                               unsigned DataSize, uint64_t Value,
>>> -                               bool IsPCRel) const {
>>> +                               unsigned DataSize, uint64_t Value, bool
>>> IsPCRel,
>>> +                               MCContext &Ctx) const {
>>>    if (Fixup.getKind() == FK_SecRel_4 || Fixup.getKind() == FK_SecRel_8)
>>> {
>>>      assert(Value == 0);
>>>    } else if (Fixup.getKind() == FK_Data_4 || Fixup.getKind() ==
>>> FK_Data_8) {
>>>
>>> Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend
>>> .cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/He
>>> xagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=299529&r1=29952
>>> 8&r2=299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
>>> Wed Apr  5 05:16:14 2017
>>> @@ -402,7 +402,8 @@ public:
>>>    /// data fragment, at the offset specified by the fixup and following
>>> the
>>>    /// fixup kind as appropriate.
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t FixupValue, bool IsPCRel) const override {
>>> +                  uint64_t FixupValue, bool IsPCRel,
>>> +                  MCContext &Ctx) const override {
>>>
>>>      // When FixupValue is 0 the relocation is external and there
>>>      // is nothing for us to do.
>>>
>>> Modified: llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/La
>>> nai/MCTargetDesc/LanaiAsmBackend.cpp?rev=299529&r1=299528&r2
>>> =299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp Wed
>>> Apr  5 05:16:14 2017
>>> @@ -50,7 +50,7 @@ public:
>>>        : MCAsmBackend(), OSType(OST) {}
>>>
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t Value, bool IsPCRel) const override;
>>> +                  uint64_t Value, bool IsPCRel, MCContext &Ctx) const
>>> override;
>>>
>>>    MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const
>>> override;
>>>
>>> @@ -90,7 +90,7 @@ bool LanaiAsmBackend::writeNopData(uint6
>>>
>>>  void LanaiAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
>>>                                   unsigned /*DataSize*/, uint64_t Value,
>>> -                                 bool /*IsPCRel*/) const {
>>> +                                 bool /*IsPCRel*/, MCContext & /*Ctx*/)
>>> const {
>>>    MCFixupKind Kind = Fixup.getKind();
>>>    Value = adjustFixupValue(static_cast<unsigned>(Kind), Value);
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mi
>>> ps/MCTargetDesc/MipsAsmBackend.cpp?rev=299529&r1=299528&r2=2
>>> 99529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Wed Apr
>>> 5 05:16:14 2017
>>> @@ -34,7 +34,7 @@ using namespace llvm;
>>>
>>>  // Prepare value for the target space for it
>>>  static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
>>> -                                 MCContext *Ctx = nullptr) {
>>> +                                 MCContext &Ctx) {
>>>
>>>    unsigned Kind = Fixup.getKind();
>>>
>>> @@ -74,8 +74,8 @@ static unsigned adjustFixupValue(const M
>>>      // address range. Forcing a signed division because Value can be
>>> negative.
>>>      Value = (int64_t)Value / 4;
>>>      // We now check if Value can be encoded as a 16-bit signed
>>> immediate.
>>> -    if (!isInt<16>(Value) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC16 fixup");
>>> +    if (!isInt<16>(Value)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>> @@ -84,8 +84,8 @@ static unsigned adjustFixupValue(const M
>>>      // Forcing a signed division because Value can be negative.
>>>      Value = (int64_t)Value / 4;
>>>      // We now check if Value can be encoded as a 19-bit signed
>>> immediate.
>>> -    if (!isInt<19>(Value) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC19 fixup");
>>> +    if (!isInt<19>(Value)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC19 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>> @@ -121,8 +121,8 @@ static unsigned adjustFixupValue(const M
>>>      // Forcing a signed division because Value can be negative.
>>>      Value = (int64_t) Value / 2;
>>>      // We now check if Value can be encoded as a 7-bit signed immediate.
>>> -    if (!isInt<7>(Value) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC7 fixup");
>>> +    if (!isInt<7>(Value)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC7 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>> @@ -131,8 +131,8 @@ static unsigned adjustFixupValue(const M
>>>      // Forcing a signed division because Value can be negative.
>>>      Value = (int64_t) Value / 2;
>>>      // We now check if Value can be encoded as a 10-bit signed
>>> immediate.
>>> -    if (!isInt<10>(Value) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC10 fixup");
>>> +    if (!isInt<10>(Value)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC10 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>> @@ -141,8 +141,8 @@ static unsigned adjustFixupValue(const M
>>>      // Forcing a signed division because Value can be negative.
>>>      Value = (int64_t)Value / 2;
>>>      // We now check if Value can be encoded as a 16-bit signed
>>> immediate.
>>> -    if (!isInt<16>(Value) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC16 fixup");
>>> +    if (!isInt<16>(Value)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>> @@ -150,21 +150,21 @@ static unsigned adjustFixupValue(const M
>>>      // Forcing a signed division because Value can be negative.
>>>      Value = (int64_t)Value / 8;
>>>      // We now check if Value can be encoded as a 18-bit signed
>>> immediate.
>>> -    if (!isInt<18>(Value) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
>>> +    if (!isInt<18>(Value)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>>    case Mips::fixup_MICROMIPS_PC18_S3:
>>>      // Check alignment.
>>> -    if ((Value & 7) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
>>> +    if ((Value & 7)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
>>>      }
>>>      // Forcing a signed division because Value can be negative.
>>>      Value = (int64_t)Value / 8;
>>>      // We now check if Value can be encoded as a 18-bit signed
>>> immediate.
>>> -    if (!isInt<18>(Value) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
>>> +    if (!isInt<18>(Value)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>> @@ -172,8 +172,8 @@ static unsigned adjustFixupValue(const M
>>>      // Forcing a signed division because Value can be negative.
>>>      Value = (int64_t) Value / 4;
>>>      // We now check if Value can be encoded as a 21-bit signed
>>> immediate.
>>> -    if (!isInt<21>(Value) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup");
>>> +    if (!isInt<21>(Value)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>> @@ -181,8 +181,8 @@ static unsigned adjustFixupValue(const M
>>>      // Forcing a signed division because Value can be negative.
>>>      Value = (int64_t) Value / 4;
>>>      // We now check if Value can be encoded as a 26-bit signed
>>> immediate.
>>> -    if (!isInt<26>(Value) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC26 fixup");
>>> +    if (!isInt<26>(Value)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>> @@ -190,8 +190,8 @@ static unsigned adjustFixupValue(const M
>>>      // Forcing a signed division because Value can be negative.
>>>      Value = (int64_t)Value / 2;
>>>      // We now check if Value can be encoded as a 26-bit signed
>>> immediate.
>>> -    if (!isInt<26>(Value) && Ctx) {
>>> -      Ctx->reportFatalError(Fixup.getLoc(), "out of range PC26 fixup");
>>> +    if (!isInt<26>(Value)) {
>>> +      Ctx.reportFatalError(Fixup.getLoc(), "out of range PC26 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>> @@ -199,8 +199,8 @@ static unsigned adjustFixupValue(const M
>>>      // Forcing a signed division because Value can be negative.
>>>      Value = (int64_t)Value / 2;
>>>      // We now check if Value can be encoded as a 21-bit signed
>>> immediate.
>>> -    if (!isInt<21>(Value) && Ctx) {
>>> -      Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup");
>>> +    if (!isInt<21>(Value)) {
>>> +      Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup");
>>>        return 0;
>>>      }
>>>      break;
>>> @@ -236,10 +236,10 @@ static unsigned calculateMMLEIndex(unsig
>>>  /// data fragment, at the offset specified by the fixup and following
>>> the
>>>  /// fixup kind as appropriate.
>>>  void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
>>> -                                unsigned DataSize, uint64_t Value,
>>> -                                bool IsPCRel) const {
>>> +                                unsigned DataSize, uint64_t Value, bool
>>> IsPCRel,
>>> +                                MCContext &Ctx) const {
>>>    MCFixupKind Kind = Fixup.getKind();
>>> -  Value = adjustFixupValue(Fixup, Value);
>>> +  Value = adjustFixupValue(Fixup, Value, Ctx);
>>>
>>>    if (!Value)
>>>      return; // Doesn't change encoding.
>>> @@ -471,24 +471,6 @@ bool MipsAsmBackend::writeNopData(uint64
>>>    return true;
>>>  }
>>>
>>> -/// processFixupValue - Target hook to process the literal value of a
>>> fixup
>>> -/// if necessary.
>>> -void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
>>> -                                       const MCAsmLayout &Layout,
>>> -                                       const MCFixup &Fixup,
>>> -                                       const MCFragment *DF,
>>> -                                       const MCValue &Target,
>>> -                                       uint64_t &Value,
>>> -                                       bool &IsResolved) {
>>> -  // At this point we'll ignore the value returned by adjustFixupValue
>>> as
>>> -  // we are only checking if the fixup can be applied correctly. We have
>>> -  // access to MCContext from here which allows us to report a fatal
>>> error
>>> -  // with *possibly* a source code location.
>>> -  // The caller will also ignore any changes we make to Value
>>> -  // (recordRelocation() overwrites it with it's own calculation).
>>> -  (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
>>> -}
>>> -
>>>  // MCAsmBackend
>>>  MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
>>>                                               const MCRegisterInfo &MRI,
>>>
>>> Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mi
>>> ps/MCTargetDesc/MipsAsmBackend.h?rev=299529&r1=299528&r2=299
>>> 529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h (original)
>>> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Wed Apr  5
>>> 05:16:14 2017
>>> @@ -39,7 +39,7 @@ public:
>>>    MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const
>>> override;
>>>
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t Value, bool IsPCRel) const override;
>>> +                  uint64_t Value, bool IsPCRel, MCContext &Ctx) const
>>> override;
>>>
>>>    Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
>>>    const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const
>>> override;
>>> @@ -82,11 +82,6 @@ public:
>>>
>>>    bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
>>>
>>> -  void processFixupValue(const MCAssembler &Asm, const MCAsmLayout
>>> &Layout,
>>> -                         const MCFixup &Fixup, const MCFragment *DF,
>>> -                         const MCValue &Target, uint64_t &Value,
>>> -                         bool &IsResolved) override;
>>> -
>>>  }; // class MipsAsmBackend
>>>
>>>  } // namespace
>>>
>>> Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Po
>>> werPC/MCTargetDesc/PPCAsmBackend.cpp?rev=299529&r1=299528&r2
>>> =299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp Wed
>>> Apr  5 05:16:14 2017
>>> @@ -114,7 +114,7 @@ public:
>>>    }
>>>
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t Value, bool IsPCRel) const override {
>>> +                  uint64_t Value, bool IsPCRel, MCContext &Ctx) const
>>> override {
>>>      Value = adjustFixupValue(Fixup.getKind(), Value);
>>>      if (!Value) return;           // Doesn't change encoding.
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RI
>>> SCV/MCTargetDesc/RISCVAsmBackend.cpp?rev=299529&r1=299528&r2
>>> =299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp Wed
>>> Apr  5 05:16:14 2017
>>> @@ -33,7 +33,7 @@ public:
>>>    ~RISCVAsmBackend() override {}
>>>
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t Value, bool IsPCRel) const override;
>>> +                  uint64_t Value, bool IsPCRel, MCContext &Ctx) const
>>> override;
>>>
>>>    MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const
>>> override;
>>>
>>> @@ -71,7 +71,7 @@ bool RISCVAsmBackend::writeNopData(uint6
>>>
>>>  void RISCVAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
>>>                                   unsigned DataSize, uint64_t Value,
>>> -                                 bool IsPCRel) const {
>>> +                                 bool IsPCRel, MCContext &Ctx) const {
>>>    return;
>>>  }
>>>
>>>
>>> Modified: llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sp
>>> arc/MCTargetDesc/SparcAsmBackend.cpp?rev=299529&r1=299528&r2
>>> =299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp Wed
>>> Apr  5 05:16:14 2017
>>> @@ -274,7 +274,8 @@ namespace {
>>>        SparcAsmBackend(T), OSType(OSType) { }
>>>
>>>      void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                    uint64_t Value, bool IsPCRel) const override {
>>> +                    uint64_t Value, bool IsPCRel,
>>> +                    MCContext &Ctx) const override {
>>>
>>>        Value = adjustFixupValue(Fixup.getKind(), Value);
>>>        if (!Value) return;           // Doesn't change encoding.
>>>
>>> Modified: llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBacke
>>> nd.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sy
>>> stemZ/MCTargetDesc/SystemZMCAsmBackend.cpp?rev=299529&r1=299
>>> 528&r2=299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
>>> (original)
>>> +++ llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
>>> Wed Apr  5 05:16:14 2017
>>> @@ -51,7 +51,7 @@ public:
>>>    }
>>>    const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const
>>> override;
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t Value, bool IsPCRel) const override;
>>> +                  uint64_t Value, bool IsPCRel, MCContext &Ctx) const
>>> override;
>>>    bool mayNeedRelaxation(const MCInst &Inst) const override {
>>>      return false;
>>>    }
>>> @@ -91,7 +91,7 @@ SystemZMCAsmBackend::getFixupKindInfo(MC
>>>
>>>  void SystemZMCAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
>>>                                       unsigned DataSize, uint64_t Value,
>>> -                                     bool IsPCRel) const {
>>> +                                     bool IsPCRel, MCContext &Ctx)
>>> const {
>>>    MCFixupKind Kind = Fixup.getKind();
>>>    unsigned Offset = Fixup.getOffset();
>>>    unsigned BitSize = getFixupKindInfo(Kind).TargetSize;
>>>
>>> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X8
>>> 6/MCTargetDesc/X86AsmBackend.cpp?rev=299529&r1=299528&r2=299
>>> 529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Wed Apr  5
>>> 05:16:14 2017
>>> @@ -109,7 +109,7 @@ public:
>>>    }
>>>
>>>    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>>> -                  uint64_t Value, bool IsPCRel) const override {
>>> +                  uint64_t Value, bool IsPCRel, MCContext &Ctx) const
>>> override {
>>>      unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
>>>
>>>      assert(Fixup.getOffset() + Size <= DataSize &&
>>>
>>> Modified: llvm/trunk/test/MC/ARM/quad-relocation.s
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/q
>>> uad-relocation.s?rev=299529&r1=299528&r2=299529&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/test/MC/ARM/quad-relocation.s (original)
>>> +++ llvm/trunk/test/MC/ARM/quad-relocation.s Wed Apr  5 05:16:14 2017
>>> @@ -4,6 +4,6 @@
>>>  symbol:
>>>    .quad(symbol)
>>>
>>> -@ CHECK: error: bad relocation fixup type
>>> +@ CHECK: error: unsupported relocation on symbol
>>>  @ CHECK-NEXT:   .quad(symbol)
>>>  @ CHECK-NEXT:        ^
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at lists.llvm.org
>>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>>>
>>
>>
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