[llvm] r299532 - [X86][SSE] Renamed combine to make it clear that it only handles the vector shift by immediate opcodes. NFCI
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 5 03:44:43 PDT 2017
Author: rksimon
Date: Wed Apr 5 05:44:42 2017
New Revision: 299532
URL: http://llvm.org/viewvc/llvm-project?rev=299532&view=rev
Log:
[X86][SSE] Renamed combine to make it clear that it only handles the vector shift by immediate opcodes. NFCI
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=299532&r1=299531&r2=299532&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Apr 5 05:44:42 2017
@@ -31258,9 +31258,9 @@ static SDValue combineShift(SDNode* N, S
return SDValue();
}
-static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG,
- TargetLowering::DAGCombinerInfo &DCI,
- const X86Subtarget &Subtarget) {
+static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
+ TargetLowering::DAGCombinerInfo &DCI,
+ const X86Subtarget &Subtarget) {
unsigned Opcode = N->getOpcode();
assert((X86ISD::VSHLI == Opcode || X86ISD::VSRAI == Opcode ||
X86ISD::VSRLI == Opcode) &&
@@ -35087,7 +35087,8 @@ SDValue X86TargetLowering::PerformDAGCom
case X86ISD::BRCOND: return combineBrCond(N, DAG, Subtarget);
case X86ISD::VSHLI:
case X86ISD::VSRAI:
- case X86ISD::VSRLI: return combineVectorShift(N, DAG, DCI, Subtarget);
+ case X86ISD::VSRLI:
+ return combineVectorShiftImm(N, DAG, DCI, Subtarget);
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
case X86ISD::VSEXT:
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