[llvm] r299487 - Allow targets to opt-in to codegen in SCC order
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 4 16:44:47 PDT 2017
Author: arsenm
Date: Tue Apr 4 18:44:46 2017
New Revision: 299487
URL: http://llvm.org/viewvc/llvm-project?rev=299487&view=rev
Log:
Allow targets to opt-in to codegen in SCC order
Decouple this setting from EnableIRPA.
To support function calls on AMDGPU, it is necessary to
report the global register usage throughout the kernel's
call graph, so callees need to be handled first.
Modified:
llvm/trunk/include/llvm/CodeGen/TargetPassConfig.h
llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
Modified: llvm/trunk/include/llvm/CodeGen/TargetPassConfig.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetPassConfig.h?rev=299487&r1=299486&r2=299487&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetPassConfig.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetPassConfig.h Tue Apr 4 18:44:46 2017
@@ -115,6 +115,10 @@ protected:
/// Default setting for -enable-tail-merge on this target.
bool EnableTailMerge;
+ /// Require processing of functions such that callees are generated before
+ /// callers.
+ bool RequireCodeGenSCCOrder;
+
public:
TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
// Dummy constructor.
@@ -162,6 +166,11 @@ public:
bool getEnableTailMerge() const { return EnableTailMerge; }
void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
+ bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
+ void setRequiresCodeGenSCCOrder(bool Enable = true) {
+ setOpt(RequireCodeGenSCCOrder, Enable);
+ }
+
/// Allow the target to override a specific pass without overriding the pass
/// pipeline. When passes are added to the standard pipeline at the
/// point where StandardID is expected, add TargetID in its place.
Modified: llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetPassConfig.cpp?rev=299487&r1=299486&r2=299487&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetPassConfig.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetPassConfig.cpp Tue Apr 4 18:44:46 2017
@@ -264,7 +264,8 @@ TargetPassConfig::~TargetPassConfig() {
TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
: ImmutablePass(ID), PM(&pm), Started(true), Stopped(false),
AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false),
- DisableVerify(false), EnableTailMerge(true) {
+ DisableVerify(false), EnableTailMerge(true),
+ RequireCodeGenSCCOrder(false) {
Impl = new PassConfigImpl();
@@ -282,6 +283,9 @@ TargetPassConfig::TargetPassConfig(Targe
if (StringRef(PrintMachineInstrs.getValue()).equals(""))
TM->Options.PrintMachineCode = true;
+
+ if (TM->Options.EnableIPRA)
+ setRequiresCodeGenSCCOrder();
}
CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
@@ -534,7 +538,7 @@ void TargetPassConfig::addISelPrepare()
addPreISel();
// Force codegen to run according to the callgraph.
- if (TM->Options.EnableIPRA)
+ if (requiresCodeGenSCCOrder())
addPass(new DummyCGSCCPass);
// Add both the safe stack and the stack protection passes: each of them will
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