[PATCH] D30539: [tablegen][globalisel] Add support for nested instruction matching.

[Daniel Sanders via Phabricator via llvm-commits]

dsanders added inline comments.


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Comment at: test/TableGen/GlobalISelEmitter.td:85
+// CHECK-NEXT:     MIB.add(MI0.getOperand(2)/*src3*/);
+// CHECK-NEXT:     MIB.setMemRefs(I.memoperands_begin(), I.memoperands_end());
+// CHECK-NEXT:     I.eraseFromParent();
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dsanders wrote:
> ab wrote:
> > On second thought, I'm not sure this is sufficient:  don't we need to merge the memops?
> I spotted another issue with this yesterday. It's unusual but some targets may choose to lower a load to a non-load and in this case we shouldn't copy the memory operands across otherwise the MachineVerifier will object.
> 
> I'll have a quick look at merging the operands.
I've made a minor change to make it merge memops from all input instructions and committed.


Repository:
  rL LLVM

https://reviews.llvm.org/D30539