[llvm] r299389 - DAG: Fix missing legalization for any_extend_vector_inreg operands
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 3 14:28:14 PDT 2017
Author: arsenm
Date: Mon Apr 3 16:28:13 2017
New Revision: 299389
URL: http://llvm.org/viewvc/llvm-project?rev=299389&view=rev
Log:
DAG: Fix missing legalization for any_extend_vector_inreg operands
Added:
llvm/trunk/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=299389&r1=299388&r2=299389&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Mon Apr 3 16:28:13 2017
@@ -678,6 +678,7 @@ private:
SDValue SplitVecOp_BITCAST(SDNode *N);
SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
+ SDValue SplitVecOp_ExtVecInRegOp(SDNode *N);
SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
SDValue SplitVecOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=299389&r1=299388&r2=299389&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Mon Apr 3 16:28:13 2017
@@ -1509,6 +1509,12 @@ bool DAGTypeLegalizer::SplitVectorOperan
case ISD::FCANONICALIZE:
Res = SplitVecOp_UnaryOp(N);
break;
+
+ case ISD::ANY_EXTEND_VECTOR_INREG:
+ case ISD::SIGN_EXTEND_VECTOR_INREG:
+ case ISD::ZERO_EXTEND_VECTOR_INREG:
+ Res = SplitVecOp_ExtVecInRegOp(N);
+ break;
}
}
@@ -1670,6 +1676,16 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXT
MachinePointerInfo(), EltVT);
}
+SDValue DAGTypeLegalizer::SplitVecOp_ExtVecInRegOp(SDNode *N) {
+ SDValue Lo, Hi;
+
+ // *_EXTEND_VECTOR_INREG only reference the lower half of the input, so
+ // splitting the result has the same effect as splitting the input operand.
+ SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
+
+ return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), N->getValueType(0), Lo, Hi);
+}
+
SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
unsigned OpNo) {
EVT LoVT, HiVT;
Added: llvm/trunk/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll?rev=299389&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll Mon Apr 3 16:28:13 2017
@@ -0,0 +1,58 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}any_extend_vector_inreg_v16i8_to_v4i32:
+; GCN: {{buffer|flat}}_load_dwordx4
+; GCN-DAG: {{buffer|flat}}_load_dwordx4
+; GCN-DAG: {{buffer|flat}}_load_dword
+
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+; GCN: {{buffer|flat}}_store_byte
+define amdgpu_kernel void @any_extend_vector_inreg_v16i8_to_v4i32(<8 x i8> addrspace(1)* nocapture readonly %arg, <16 x i8> addrspace(1)* %arg1) local_unnamed_addr #0 {
+bb:
+ %tmp = bitcast <8 x i8> addrspace(1)* %arg to <16 x i8> addrspace(1)*
+ %tmp2 = load <16 x i8>, <16 x i8> addrspace(1)* %tmp, align 16
+ %tmp3 = extractelement <16 x i8> %tmp2, i64 4
+ %tmp6 = extractelement <16 x i8> %tmp2, i64 11
+ %tmp10 = getelementptr inbounds <8 x i8>, <8 x i8> addrspace(1)* %arg, i64 2
+ %tmp11 = bitcast <8 x i8> addrspace(1)* %tmp10 to <16 x i8> addrspace(1)*
+ %tmp12 = load <16 x i8>, <16 x i8> addrspace(1)* %tmp11, align 16
+ %tmp13 = extractelement <16 x i8> %tmp12, i64 7
+ %tmp17 = extractelement <16 x i8> %tmp12, i64 12
+ %tmp21 = getelementptr inbounds <8 x i8>, <8 x i8> addrspace(1)* %arg, i64 4
+ %tmp22 = bitcast <8 x i8> addrspace(1)* %tmp21 to <16 x i8> addrspace(1)*
+ %tmp23 = load <16 x i8>, <16 x i8> addrspace(1)* %tmp22, align 16
+ %tmp24 = extractelement <16 x i8> %tmp23, i64 3
+ %tmp1 = insertelement <16 x i8> undef, i8 %tmp3, i32 2
+ %tmp4 = insertelement <16 x i8> %tmp1, i8 0, i32 3
+ %tmp5 = insertelement <16 x i8> %tmp4, i8 0, i32 4
+ %tmp7 = insertelement <16 x i8> %tmp5, i8 %tmp6, i32 5
+ %tmp8 = insertelement <16 x i8> %tmp7, i8 0, i32 6
+ %tmp9 = insertelement <16 x i8> %tmp8, i8 %tmp13, i32 7
+ %tmp14 = insertelement <16 x i8> %tmp9, i8 0, i32 8
+ %tmp15 = insertelement <16 x i8> %tmp14, i8 %tmp17, i32 9
+ %tmp16 = insertelement <16 x i8> %tmp15, i8 0, i32 10
+ %tmp18 = insertelement <16 x i8> %tmp16, i8 0, i32 11
+ %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp24, i32 12
+ store <16 x i8> %tmp19, <16 x i8> addrspace(1)* %arg1, align 1
+ ret void
+}
+
+attributes #0 = { nounwind }
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