[PATCH] D31331: [mips][msa] Truncation of vector elements for instructions creating ISD::SHL, ISD::SRL or ISD::SRA nodes

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: lib/Target/Mips/MipsSEISelLowering.cpp:1556-1560
+  SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1,
+                                       DL, ResEltTy);
+  SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
+
+  return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
----------------
sdardis wrote:
> This hunk only covers the non-constant case. When the operand to a logical ISD vector node--which implicitly masks the lower bits--is a ConstantSDnode, we should instead reformulate the constant so that it only contains bits that the MSA instructions will look at. 
Doesn't constant folding cover the constant case?


https://reviews.llvm.org/D31331