[llvm] r299284 - Instrument SDISel C++ patterns

Quentin Colombet via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 31 18:21:32 PDT 2017


Author: qcolombet
Date: Fri Mar 31 20:21:32 2017
New Revision: 299284

URL: http://llvm.org/viewvc/llvm-project?rev=299284&view=rev
Log:
Instrument SDISel C++ patterns

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
    llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
    llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp?rev=299284&r1=299283&r2=299284&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp Fri Mar 31 20:21:32 2017
@@ -371,7 +371,6 @@ static Printable PrintNodeId(const SDNod
 LLVM_DUMP_METHOD void SDNode::dump() const { dump(nullptr); }
 LLVM_DUMP_METHOD void SDNode::dump(const SelectionDAG *G) const {
   print(dbgs(), G);
-  dbgs() << '\n';
 }
 #endif
 

Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=299284&r1=299283&r2=299284&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Fri Mar 31 20:21:32 2017
@@ -63,6 +63,7 @@
 #include "llvm/Support/AtomicOrdering.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CodeGen.h"
+#include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include <algorithm>
@@ -71,6 +72,7 @@
 #include <iterator>
 #include <utility>
 
+#define DEBUG_TYPE "aarch64-fastisel"
 using namespace llvm;
 
 namespace {
@@ -5048,85 +5050,92 @@ bool AArch64FastISel::selectAtomicCmpXch
   return true;
 }
 
+#define ReturnSelect(expr) do {                                         \
+    bool Selected ## __LINE__ =  expr;                                  \
+    if (Selected ## __LINE__)                                           \
+      DEBUG(dbgs() << "FastISel Selected: " << *I << '\n');             \
+    return Selected ## __LINE__;                                        \
+  } while(0)
+
 bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
   switch (I->getOpcode()) {
   default:
     break;
   case Instruction::Add:
   case Instruction::Sub:
-    return selectAddSub(I);
+    ReturnSelect(selectAddSub(I));
   case Instruction::Mul:
-    return selectMul(I);
+    ReturnSelect(selectMul(I));
   case Instruction::SDiv:
-    return selectSDiv(I);
+    ReturnSelect(selectSDiv(I));
   case Instruction::SRem:
     if (!selectBinaryOp(I, ISD::SREM))
-      return selectRem(I, ISD::SREM);
-    return true;
+      ReturnSelect(selectRem(I, ISD::SREM));
+    ReturnSelect(true);
   case Instruction::URem:
     if (!selectBinaryOp(I, ISD::UREM))
-      return selectRem(I, ISD::UREM);
-    return true;
+      ReturnSelect(selectRem(I, ISD::UREM));
+    ReturnSelect(true);
   case Instruction::Shl:
   case Instruction::LShr:
   case Instruction::AShr:
-    return selectShift(I);
+    ReturnSelect(selectShift(I));
   case Instruction::And:
   case Instruction::Or:
   case Instruction::Xor:
-    return selectLogicalOp(I);
+    ReturnSelect(selectLogicalOp(I));
   case Instruction::Br:
-    return selectBranch(I);
+    ReturnSelect(selectBranch(I));
   case Instruction::IndirectBr:
-    return selectIndirectBr(I);
+    ReturnSelect(selectIndirectBr(I));
   case Instruction::BitCast:
     if (!FastISel::selectBitCast(I))
-      return selectBitCast(I);
-    return true;
+      ReturnSelect(selectBitCast(I));
+    ReturnSelect(true);
   case Instruction::FPToSI:
     if (!selectCast(I, ISD::FP_TO_SINT))
-      return selectFPToInt(I, /*Signed=*/true);
-    return true;
+      ReturnSelect(selectFPToInt(I, /*Signed=*/true));
+    ReturnSelect(true);
   case Instruction::FPToUI:
-    return selectFPToInt(I, /*Signed=*/false);
+    ReturnSelect(selectFPToInt(I, /*Signed=*/false));
   case Instruction::ZExt:
   case Instruction::SExt:
-    return selectIntExt(I);
+    ReturnSelect(selectIntExt(I));
   case Instruction::Trunc:
     if (!selectCast(I, ISD::TRUNCATE))
-      return selectTrunc(I);
-    return true;
+      ReturnSelect(selectTrunc(I));
+    ReturnSelect(true);
   case Instruction::FPExt:
-    return selectFPExt(I);
+    ReturnSelect(selectFPExt(I));
   case Instruction::FPTrunc:
-    return selectFPTrunc(I);
+    ReturnSelect(selectFPTrunc(I));
   case Instruction::SIToFP:
     if (!selectCast(I, ISD::SINT_TO_FP))
-      return selectIntToFP(I, /*Signed=*/true);
-    return true;
+      ReturnSelect(selectIntToFP(I, /*Signed=*/true));
+    ReturnSelect(true);
   case Instruction::UIToFP:
-    return selectIntToFP(I, /*Signed=*/false);
+    ReturnSelect(selectIntToFP(I, /*Signed=*/false));
   case Instruction::Load:
-    return selectLoad(I);
+    ReturnSelect(selectLoad(I));
   case Instruction::Store:
-    return selectStore(I);
+    ReturnSelect(selectStore(I));
   case Instruction::FCmp:
   case Instruction::ICmp:
-    return selectCmp(I);
+    ReturnSelect(selectCmp(I));
   case Instruction::Select:
-    return selectSelect(I);
+    ReturnSelect(selectSelect(I));
   case Instruction::Ret:
-    return selectRet(I);
+    ReturnSelect(selectRet(I));
   case Instruction::FRem:
-    return selectFRem(I);
+    ReturnSelect(selectFRem(I));
   case Instruction::GetElementPtr:
-    return selectGetElementPtr(I);
+    ReturnSelect(selectGetElementPtr(I));
   case Instruction::AtomicCmpXchg:
-    return selectAtomicCmpXchg(cast<AtomicCmpXchgInst>(I));
+    ReturnSelect(selectAtomicCmpXchg(cast<AtomicCmpXchgInst>(I)));
   }
 
   // fall-back to target-independent instruction selection.
-  return selectOperator(I, I->getOpcode());
+  ReturnSelect(selectOperator(I, I->getOpcode()));
   // Silence warnings.
   (void)&CC_AArch64_DarwinPCS_VarArg;
 }

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=299284&r1=299283&r2=299284&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Fri Mar 31 20:21:32 2017
@@ -2638,6 +2638,9 @@ void AArch64DAGToDAGISel::SelectCMP_SWAP
   CurDAG->RemoveDeadNode(N);
 }
 
+
+#define ReturnSelected(Node) do { DEBUG(dbgs() << " succeeded " << __LINE__ << " \n"); return;} while(0)
+
 void AArch64DAGToDAGISel::Select(SDNode *Node) {
   // Dump information about the Node being selected
   DEBUG(errs() << "Selecting: ");
@@ -2654,34 +2657,36 @@ void AArch64DAGToDAGISel::Select(SDNode
   // Few custom selection stuff.
   EVT VT = Node->getValueType(0);
 
+  DEBUG(dbgs() << "Custom Select: "; Node->dump());
+  
   switch (Node->getOpcode()) {
   default:
     break;
 
   case ISD::ATOMIC_CMP_SWAP:
     SelectCMP_SWAP(Node);
-    return;
+    ReturnSelected(Node);
 
   case ISD::READ_REGISTER:
     if (tryReadRegister(Node))
-      return;
+      ReturnSelected(Node);
     break;
 
   case ISD::WRITE_REGISTER:
     if (tryWriteRegister(Node))
-      return;
+      ReturnSelected(Node);
     break;
 
   case ISD::ADD:
     if (tryMLAV64LaneV128(Node))
-      return;
+      ReturnSelected(Node);
     break;
 
   case ISD::LOAD: {
     // Try to select as an indexed load. Fall through to normal processing
     // if we can't.
     if (tryIndexedLoad(Node))
-      return;
+      ReturnSelected(Node);
     break;
   }
 
@@ -2690,19 +2695,19 @@ void AArch64DAGToDAGISel::Select(SDNode
   case ISD::SRA:
   case ISD::SIGN_EXTEND_INREG:
     if (tryBitfieldExtractOp(Node))
-      return;
+      ReturnSelected(Node);
     if (tryBitfieldInsertInZeroOp(Node))
-      return;
+      ReturnSelected(Node);
     break;
 
   case ISD::SIGN_EXTEND:
     if (tryBitfieldExtractOpFromSExt(Node))
-      return;
+      ReturnSelected(Node);
     break;
 
   case ISD::OR:
     if (tryBitfieldInsertOp(Node))
-      return;
+      ReturnSelected(Node);
     break;
 
   case ISD::EXTRACT_VECTOR_ELT: {
@@ -2746,7 +2751,7 @@ void AArch64DAGToDAGISel::Select(SDNode
     DEBUG(Extract->dumpr(CurDAG));
     DEBUG(dbgs() << "\n");
     ReplaceNode(Node, Extract.getNode());
-    return;
+    ReturnSelected(Node);
   }
   case ISD::Constant: {
     // Materialize zero constants as copies from WZR/XZR.  This allows
@@ -2757,12 +2762,12 @@ void AArch64DAGToDAGISel::Select(SDNode
         SDValue New = CurDAG->getCopyFromReg(
             CurDAG->getEntryNode(), SDLoc(Node), AArch64::WZR, MVT::i32);
         ReplaceNode(Node, New.getNode());
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::i64) {
         SDValue New = CurDAG->getCopyFromReg(
             CurDAG->getEntryNode(), SDLoc(Node), AArch64::XZR, MVT::i64);
         ReplaceNode(Node, New.getNode());
-        return;
+        ReturnSelected(Node);
       }
     }
     break;
@@ -2779,7 +2784,7 @@ void AArch64DAGToDAGISel::Select(SDNode
     SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, DL, MVT::i32),
                       CurDAG->getTargetConstant(Shifter, DL, MVT::i32) };
     CurDAG->SelectNodeTo(Node, AArch64::ADDXri, MVT::i64, Ops);
-    return;
+    ReturnSelected(Node);
   }
   case ISD::INTRINSIC_W_CHAIN: {
     unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
@@ -2802,7 +2807,7 @@ void AArch64DAGToDAGISel::Select(SDNode
       MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
       cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
       ReplaceNode(Node, Ld);
-      return;
+      ReturnSelected(Node);
     }
     case Intrinsic::aarch64_stlxp:
     case Intrinsic::aarch64_stxp: {
@@ -2824,303 +2829,303 @@ void AArch64DAGToDAGISel::Select(SDNode
       cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
 
       ReplaceNode(Node, St);
-      return;
+      ReturnSelected(Node);
     }
     case Intrinsic::aarch64_neon_ld1x2:
       if (VT == MVT::v8i8) {
         SelectLoad(Node, 2, AArch64::LD1Twov8b, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectLoad(Node, 2, AArch64::LD1Twov16b, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectLoad(Node, 2, AArch64::LD1Twov4h, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectLoad(Node, 2, AArch64::LD1Twov8h, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectLoad(Node, 2, AArch64::LD1Twov2s, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectLoad(Node, 2, AArch64::LD1Twov4s, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectLoad(Node, 2, AArch64::LD1Twov2d, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld1x3:
       if (VT == MVT::v8i8) {
         SelectLoad(Node, 3, AArch64::LD1Threev8b, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectLoad(Node, 3, AArch64::LD1Threev16b, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectLoad(Node, 3, AArch64::LD1Threev4h, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectLoad(Node, 3, AArch64::LD1Threev8h, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectLoad(Node, 3, AArch64::LD1Threev2s, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectLoad(Node, 3, AArch64::LD1Threev4s, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectLoad(Node, 3, AArch64::LD1Threev2d, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld1x4:
       if (VT == MVT::v8i8) {
         SelectLoad(Node, 4, AArch64::LD1Fourv8b, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectLoad(Node, 4, AArch64::LD1Fourv16b, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectLoad(Node, 4, AArch64::LD1Fourv4h, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectLoad(Node, 4, AArch64::LD1Fourv8h, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectLoad(Node, 4, AArch64::LD1Fourv2s, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectLoad(Node, 4, AArch64::LD1Fourv4s, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectLoad(Node, 4, AArch64::LD1Fourv2d, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld2:
       if (VT == MVT::v8i8) {
         SelectLoad(Node, 2, AArch64::LD2Twov8b, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectLoad(Node, 2, AArch64::LD2Twov16b, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectLoad(Node, 2, AArch64::LD2Twov4h, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectLoad(Node, 2, AArch64::LD2Twov8h, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectLoad(Node, 2, AArch64::LD2Twov2s, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectLoad(Node, 2, AArch64::LD2Twov4s, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectLoad(Node, 2, AArch64::LD1Twov1d, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectLoad(Node, 2, AArch64::LD2Twov2d, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld3:
       if (VT == MVT::v8i8) {
         SelectLoad(Node, 3, AArch64::LD3Threev8b, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectLoad(Node, 3, AArch64::LD3Threev16b, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectLoad(Node, 3, AArch64::LD3Threev4h, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectLoad(Node, 3, AArch64::LD3Threev8h, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectLoad(Node, 3, AArch64::LD3Threev2s, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectLoad(Node, 3, AArch64::LD3Threev4s, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectLoad(Node, 3, AArch64::LD1Threev1d, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectLoad(Node, 3, AArch64::LD3Threev2d, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld4:
       if (VT == MVT::v8i8) {
         SelectLoad(Node, 4, AArch64::LD4Fourv8b, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectLoad(Node, 4, AArch64::LD4Fourv16b, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectLoad(Node, 4, AArch64::LD4Fourv4h, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectLoad(Node, 4, AArch64::LD4Fourv8h, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectLoad(Node, 4, AArch64::LD4Fourv2s, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectLoad(Node, 4, AArch64::LD4Fourv4s, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectLoad(Node, 4, AArch64::LD1Fourv1d, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectLoad(Node, 4, AArch64::LD4Fourv2d, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld2r:
       if (VT == MVT::v8i8) {
         SelectLoad(Node, 2, AArch64::LD2Rv8b, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectLoad(Node, 2, AArch64::LD2Rv16b, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectLoad(Node, 2, AArch64::LD2Rv4h, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectLoad(Node, 2, AArch64::LD2Rv8h, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectLoad(Node, 2, AArch64::LD2Rv2s, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectLoad(Node, 2, AArch64::LD2Rv4s, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectLoad(Node, 2, AArch64::LD2Rv1d, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectLoad(Node, 2, AArch64::LD2Rv2d, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld3r:
       if (VT == MVT::v8i8) {
         SelectLoad(Node, 3, AArch64::LD3Rv8b, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectLoad(Node, 3, AArch64::LD3Rv16b, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectLoad(Node, 3, AArch64::LD3Rv4h, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectLoad(Node, 3, AArch64::LD3Rv8h, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectLoad(Node, 3, AArch64::LD3Rv2s, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectLoad(Node, 3, AArch64::LD3Rv4s, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectLoad(Node, 3, AArch64::LD3Rv1d, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectLoad(Node, 3, AArch64::LD3Rv2d, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld4r:
       if (VT == MVT::v8i8) {
         SelectLoad(Node, 4, AArch64::LD4Rv8b, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectLoad(Node, 4, AArch64::LD4Rv16b, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectLoad(Node, 4, AArch64::LD4Rv4h, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectLoad(Node, 4, AArch64::LD4Rv8h, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectLoad(Node, 4, AArch64::LD4Rv2s, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectLoad(Node, 4, AArch64::LD4Rv4s, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectLoad(Node, 4, AArch64::LD4Rv1d, AArch64::dsub0);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectLoad(Node, 4, AArch64::LD4Rv2d, AArch64::qsub0);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld2lane:
       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
         SelectLoadLane(Node, 2, AArch64::LD2i8);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                  VT == MVT::v8f16) {
         SelectLoadLane(Node, 2, AArch64::LD2i16);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                  VT == MVT::v2f32) {
         SelectLoadLane(Node, 2, AArch64::LD2i32);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                  VT == MVT::v1f64) {
         SelectLoadLane(Node, 2, AArch64::LD2i64);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld3lane:
       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
         SelectLoadLane(Node, 3, AArch64::LD3i8);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                  VT == MVT::v8f16) {
         SelectLoadLane(Node, 3, AArch64::LD3i16);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                  VT == MVT::v2f32) {
         SelectLoadLane(Node, 3, AArch64::LD3i32);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                  VT == MVT::v1f64) {
         SelectLoadLane(Node, 3, AArch64::LD3i64);
-        return;
+        ReturnSelected(Node);
       }
       break;
     case Intrinsic::aarch64_neon_ld4lane:
       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
         SelectLoadLane(Node, 4, AArch64::LD4i8);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                  VT == MVT::v8f16) {
         SelectLoadLane(Node, 4, AArch64::LD4i16);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                  VT == MVT::v2f32) {
         SelectLoadLane(Node, 4, AArch64::LD4i32);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                  VT == MVT::v1f64) {
         SelectLoadLane(Node, 4, AArch64::LD4i64);
-        return;
+        ReturnSelected(Node);
       }
       break;
     }
@@ -3134,36 +3139,36 @@ void AArch64DAGToDAGISel::Select(SDNode
       SelectTable(Node, 2,
                   VT == MVT::v8i8 ? AArch64::TBLv8i8Two : AArch64::TBLv16i8Two,
                   false);
-      return;
+      ReturnSelected(Node);
     case Intrinsic::aarch64_neon_tbl3:
       SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBLv8i8Three
                                            : AArch64::TBLv16i8Three,
                   false);
-      return;
+      ReturnSelected(Node);
     case Intrinsic::aarch64_neon_tbl4:
       SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBLv8i8Four
                                            : AArch64::TBLv16i8Four,
                   false);
-      return;
+      ReturnSelected(Node);
     case Intrinsic::aarch64_neon_tbx2:
       SelectTable(Node, 2,
                   VT == MVT::v8i8 ? AArch64::TBXv8i8Two : AArch64::TBXv16i8Two,
                   true);
-      return;
+      ReturnSelected(Node);
     case Intrinsic::aarch64_neon_tbx3:
       SelectTable(Node, 3, VT == MVT::v8i8 ? AArch64::TBXv8i8Three
                                            : AArch64::TBXv16i8Three,
                   true);
-      return;
+      ReturnSelected(Node);
     case Intrinsic::aarch64_neon_tbx4:
       SelectTable(Node, 4, VT == MVT::v8i8 ? AArch64::TBXv8i8Four
                                            : AArch64::TBXv16i8Four,
                   true);
-      return;
+      ReturnSelected(Node);
     case Intrinsic::aarch64_neon_smull:
     case Intrinsic::aarch64_neon_umull:
       if (tryMULLV64LaneV128(IntNo, Node))
-        return;
+        ReturnSelected(Node);
       break;
     }
     break;
@@ -3178,225 +3183,225 @@ void AArch64DAGToDAGISel::Select(SDNode
     case Intrinsic::aarch64_neon_st1x2: {
       if (VT == MVT::v8i8) {
         SelectStore(Node, 2, AArch64::ST1Twov8b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectStore(Node, 2, AArch64::ST1Twov16b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectStore(Node, 2, AArch64::ST1Twov4h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectStore(Node, 2, AArch64::ST1Twov8h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectStore(Node, 2, AArch64::ST1Twov2s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectStore(Node, 2, AArch64::ST1Twov4s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectStore(Node, 2, AArch64::ST1Twov2d);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectStore(Node, 2, AArch64::ST1Twov1d);
-        return;
+        ReturnSelected(Node);
       }
       break;
     }
     case Intrinsic::aarch64_neon_st1x3: {
       if (VT == MVT::v8i8) {
         SelectStore(Node, 3, AArch64::ST1Threev8b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectStore(Node, 3, AArch64::ST1Threev16b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectStore(Node, 3, AArch64::ST1Threev4h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectStore(Node, 3, AArch64::ST1Threev8h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectStore(Node, 3, AArch64::ST1Threev2s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectStore(Node, 3, AArch64::ST1Threev4s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectStore(Node, 3, AArch64::ST1Threev2d);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectStore(Node, 3, AArch64::ST1Threev1d);
-        return;
+        ReturnSelected(Node);
       }
       break;
     }
     case Intrinsic::aarch64_neon_st1x4: {
       if (VT == MVT::v8i8) {
         SelectStore(Node, 4, AArch64::ST1Fourv8b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectStore(Node, 4, AArch64::ST1Fourv16b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectStore(Node, 4, AArch64::ST1Fourv4h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectStore(Node, 4, AArch64::ST1Fourv8h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectStore(Node, 4, AArch64::ST1Fourv2s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectStore(Node, 4, AArch64::ST1Fourv4s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectStore(Node, 4, AArch64::ST1Fourv2d);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectStore(Node, 4, AArch64::ST1Fourv1d);
-        return;
+        ReturnSelected(Node);
       }
       break;
     }
     case Intrinsic::aarch64_neon_st2: {
       if (VT == MVT::v8i8) {
         SelectStore(Node, 2, AArch64::ST2Twov8b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectStore(Node, 2, AArch64::ST2Twov16b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectStore(Node, 2, AArch64::ST2Twov4h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectStore(Node, 2, AArch64::ST2Twov8h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectStore(Node, 2, AArch64::ST2Twov2s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectStore(Node, 2, AArch64::ST2Twov4s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectStore(Node, 2, AArch64::ST2Twov2d);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectStore(Node, 2, AArch64::ST1Twov1d);
-        return;
+        ReturnSelected(Node);
       }
       break;
     }
     case Intrinsic::aarch64_neon_st3: {
       if (VT == MVT::v8i8) {
         SelectStore(Node, 3, AArch64::ST3Threev8b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectStore(Node, 3, AArch64::ST3Threev16b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectStore(Node, 3, AArch64::ST3Threev4h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectStore(Node, 3, AArch64::ST3Threev8h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectStore(Node, 3, AArch64::ST3Threev2s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectStore(Node, 3, AArch64::ST3Threev4s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectStore(Node, 3, AArch64::ST3Threev2d);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectStore(Node, 3, AArch64::ST1Threev1d);
-        return;
+        ReturnSelected(Node);
       }
       break;
     }
     case Intrinsic::aarch64_neon_st4: {
       if (VT == MVT::v8i8) {
         SelectStore(Node, 4, AArch64::ST4Fourv8b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v16i8) {
         SelectStore(Node, 4, AArch64::ST4Fourv16b);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
         SelectStore(Node, 4, AArch64::ST4Fourv4h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
         SelectStore(Node, 4, AArch64::ST4Fourv8h);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
         SelectStore(Node, 4, AArch64::ST4Fourv2s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
         SelectStore(Node, 4, AArch64::ST4Fourv4s);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
         SelectStore(Node, 4, AArch64::ST4Fourv2d);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
         SelectStore(Node, 4, AArch64::ST1Fourv1d);
-        return;
+        ReturnSelected(Node);
       }
       break;
     }
     case Intrinsic::aarch64_neon_st2lane: {
       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
         SelectStoreLane(Node, 2, AArch64::ST2i8);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                  VT == MVT::v8f16) {
         SelectStoreLane(Node, 2, AArch64::ST2i16);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                  VT == MVT::v2f32) {
         SelectStoreLane(Node, 2, AArch64::ST2i32);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                  VT == MVT::v1f64) {
         SelectStoreLane(Node, 2, AArch64::ST2i64);
-        return;
+        ReturnSelected(Node);
       }
       break;
     }
     case Intrinsic::aarch64_neon_st3lane: {
       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
         SelectStoreLane(Node, 3, AArch64::ST3i8);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                  VT == MVT::v8f16) {
         SelectStoreLane(Node, 3, AArch64::ST3i16);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                  VT == MVT::v2f32) {
         SelectStoreLane(Node, 3, AArch64::ST3i32);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                  VT == MVT::v1f64) {
         SelectStoreLane(Node, 3, AArch64::ST3i64);
-        return;
+        ReturnSelected(Node);
       }
       break;
     }
     case Intrinsic::aarch64_neon_st4lane: {
       if (VT == MVT::v16i8 || VT == MVT::v8i8) {
         SelectStoreLane(Node, 4, AArch64::ST4i8);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                  VT == MVT::v8f16) {
         SelectStoreLane(Node, 4, AArch64::ST4i16);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                  VT == MVT::v2f32) {
         SelectStoreLane(Node, 4, AArch64::ST4i32);
-        return;
+        ReturnSelected(Node);
       } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                  VT == MVT::v1f64) {
         SelectStoreLane(Node, 4, AArch64::ST4i64);
-        return;
+        ReturnSelected(Node);
       }
       break;
     }
@@ -3406,356 +3411,356 @@ void AArch64DAGToDAGISel::Select(SDNode
   case AArch64ISD::LD2post: {
     if (VT == MVT::v8i8) {
       SelectPostLoad(Node, 2, AArch64::LD2Twov8b_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostLoad(Node, 2, AArch64::LD2Twov16b_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostLoad(Node, 2, AArch64::LD2Twov4h_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostLoad(Node, 2, AArch64::LD2Twov8h_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostLoad(Node, 2, AArch64::LD2Twov2s_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostLoad(Node, 2, AArch64::LD2Twov4s_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostLoad(Node, 2, AArch64::LD2Twov2d_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD3post: {
     if (VT == MVT::v8i8) {
       SelectPostLoad(Node, 3, AArch64::LD3Threev8b_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostLoad(Node, 3, AArch64::LD3Threev16b_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostLoad(Node, 3, AArch64::LD3Threev4h_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostLoad(Node, 3, AArch64::LD3Threev8h_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostLoad(Node, 3, AArch64::LD3Threev2s_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostLoad(Node, 3, AArch64::LD3Threev4s_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostLoad(Node, 3, AArch64::LD3Threev2d_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD4post: {
     if (VT == MVT::v8i8) {
       SelectPostLoad(Node, 4, AArch64::LD4Fourv8b_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostLoad(Node, 4, AArch64::LD4Fourv16b_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostLoad(Node, 4, AArch64::LD4Fourv4h_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostLoad(Node, 4, AArch64::LD4Fourv8h_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostLoad(Node, 4, AArch64::LD4Fourv2s_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostLoad(Node, 4, AArch64::LD4Fourv4s_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostLoad(Node, 4, AArch64::LD4Fourv2d_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD1x2post: {
     if (VT == MVT::v8i8) {
       SelectPostLoad(Node, 2, AArch64::LD1Twov8b_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostLoad(Node, 2, AArch64::LD1Twov16b_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostLoad(Node, 2, AArch64::LD1Twov4h_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostLoad(Node, 2, AArch64::LD1Twov8h_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostLoad(Node, 2, AArch64::LD1Twov2s_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostLoad(Node, 2, AArch64::LD1Twov4s_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostLoad(Node, 2, AArch64::LD1Twov1d_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostLoad(Node, 2, AArch64::LD1Twov2d_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD1x3post: {
     if (VT == MVT::v8i8) {
       SelectPostLoad(Node, 3, AArch64::LD1Threev8b_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostLoad(Node, 3, AArch64::LD1Threev16b_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostLoad(Node, 3, AArch64::LD1Threev4h_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostLoad(Node, 3, AArch64::LD1Threev8h_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostLoad(Node, 3, AArch64::LD1Threev2s_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostLoad(Node, 3, AArch64::LD1Threev4s_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostLoad(Node, 3, AArch64::LD1Threev1d_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostLoad(Node, 3, AArch64::LD1Threev2d_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD1x4post: {
     if (VT == MVT::v8i8) {
       SelectPostLoad(Node, 4, AArch64::LD1Fourv8b_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostLoad(Node, 4, AArch64::LD1Fourv16b_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostLoad(Node, 4, AArch64::LD1Fourv4h_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostLoad(Node, 4, AArch64::LD1Fourv8h_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostLoad(Node, 4, AArch64::LD1Fourv2s_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostLoad(Node, 4, AArch64::LD1Fourv4s_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostLoad(Node, 4, AArch64::LD1Fourv2d_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD1DUPpost: {
     if (VT == MVT::v8i8) {
       SelectPostLoad(Node, 1, AArch64::LD1Rv8b_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostLoad(Node, 1, AArch64::LD1Rv16b_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostLoad(Node, 1, AArch64::LD1Rv4h_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostLoad(Node, 1, AArch64::LD1Rv8h_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostLoad(Node, 1, AArch64::LD1Rv2s_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostLoad(Node, 1, AArch64::LD1Rv4s_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostLoad(Node, 1, AArch64::LD1Rv1d_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostLoad(Node, 1, AArch64::LD1Rv2d_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD2DUPpost: {
     if (VT == MVT::v8i8) {
       SelectPostLoad(Node, 2, AArch64::LD2Rv8b_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostLoad(Node, 2, AArch64::LD2Rv16b_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostLoad(Node, 2, AArch64::LD2Rv4h_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostLoad(Node, 2, AArch64::LD2Rv8h_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostLoad(Node, 2, AArch64::LD2Rv2s_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostLoad(Node, 2, AArch64::LD2Rv4s_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostLoad(Node, 2, AArch64::LD2Rv1d_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostLoad(Node, 2, AArch64::LD2Rv2d_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD3DUPpost: {
     if (VT == MVT::v8i8) {
       SelectPostLoad(Node, 3, AArch64::LD3Rv8b_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostLoad(Node, 3, AArch64::LD3Rv16b_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostLoad(Node, 3, AArch64::LD3Rv4h_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostLoad(Node, 3, AArch64::LD3Rv8h_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostLoad(Node, 3, AArch64::LD3Rv2s_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostLoad(Node, 3, AArch64::LD3Rv4s_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostLoad(Node, 3, AArch64::LD3Rv1d_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostLoad(Node, 3, AArch64::LD3Rv2d_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD4DUPpost: {
     if (VT == MVT::v8i8) {
       SelectPostLoad(Node, 4, AArch64::LD4Rv8b_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostLoad(Node, 4, AArch64::LD4Rv16b_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostLoad(Node, 4, AArch64::LD4Rv4h_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostLoad(Node, 4, AArch64::LD4Rv8h_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostLoad(Node, 4, AArch64::LD4Rv2s_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostLoad(Node, 4, AArch64::LD4Rv4s_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostLoad(Node, 4, AArch64::LD4Rv1d_POST, AArch64::dsub0);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostLoad(Node, 4, AArch64::LD4Rv2d_POST, AArch64::qsub0);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD1LANEpost: {
     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
       SelectPostLoadLane(Node, 1, AArch64::LD1i8_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                VT == MVT::v8f16) {
       SelectPostLoadLane(Node, 1, AArch64::LD1i16_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                VT == MVT::v2f32) {
       SelectPostLoadLane(Node, 1, AArch64::LD1i32_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                VT == MVT::v1f64) {
       SelectPostLoadLane(Node, 1, AArch64::LD1i64_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD2LANEpost: {
     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
       SelectPostLoadLane(Node, 2, AArch64::LD2i8_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                VT == MVT::v8f16) {
       SelectPostLoadLane(Node, 2, AArch64::LD2i16_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                VT == MVT::v2f32) {
       SelectPostLoadLane(Node, 2, AArch64::LD2i32_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                VT == MVT::v1f64) {
       SelectPostLoadLane(Node, 2, AArch64::LD2i64_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD3LANEpost: {
     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
       SelectPostLoadLane(Node, 3, AArch64::LD3i8_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                VT == MVT::v8f16) {
       SelectPostLoadLane(Node, 3, AArch64::LD3i16_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                VT == MVT::v2f32) {
       SelectPostLoadLane(Node, 3, AArch64::LD3i32_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                VT == MVT::v1f64) {
       SelectPostLoadLane(Node, 3, AArch64::LD3i64_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
   case AArch64ISD::LD4LANEpost: {
     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
       SelectPostLoadLane(Node, 4, AArch64::LD4i8_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                VT == MVT::v8f16) {
       SelectPostLoadLane(Node, 4, AArch64::LD4i16_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                VT == MVT::v2f32) {
       SelectPostLoadLane(Node, 4, AArch64::LD4i32_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                VT == MVT::v1f64) {
       SelectPostLoadLane(Node, 4, AArch64::LD4i64_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
@@ -3763,28 +3768,28 @@ void AArch64DAGToDAGISel::Select(SDNode
     VT = Node->getOperand(1).getValueType();
     if (VT == MVT::v8i8) {
       SelectPostStore(Node, 2, AArch64::ST2Twov8b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostStore(Node, 2, AArch64::ST2Twov16b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostStore(Node, 2, AArch64::ST2Twov4h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostStore(Node, 2, AArch64::ST2Twov8h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostStore(Node, 2, AArch64::ST2Twov2s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostStore(Node, 2, AArch64::ST2Twov4s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostStore(Node, 2, AArch64::ST2Twov2d_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
@@ -3792,28 +3797,28 @@ void AArch64DAGToDAGISel::Select(SDNode
     VT = Node->getOperand(1).getValueType();
     if (VT == MVT::v8i8) {
       SelectPostStore(Node, 3, AArch64::ST3Threev8b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostStore(Node, 3, AArch64::ST3Threev16b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostStore(Node, 3, AArch64::ST3Threev4h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostStore(Node, 3, AArch64::ST3Threev8h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostStore(Node, 3, AArch64::ST3Threev2s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostStore(Node, 3, AArch64::ST3Threev4s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostStore(Node, 3, AArch64::ST3Threev2d_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
@@ -3821,28 +3826,28 @@ void AArch64DAGToDAGISel::Select(SDNode
     VT = Node->getOperand(1).getValueType();
     if (VT == MVT::v8i8) {
       SelectPostStore(Node, 4, AArch64::ST4Fourv8b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostStore(Node, 4, AArch64::ST4Fourv16b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostStore(Node, 4, AArch64::ST4Fourv4h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostStore(Node, 4, AArch64::ST4Fourv8h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostStore(Node, 4, AArch64::ST4Fourv2s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostStore(Node, 4, AArch64::ST4Fourv4s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostStore(Node, 4, AArch64::ST4Fourv2d_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
@@ -3850,28 +3855,28 @@ void AArch64DAGToDAGISel::Select(SDNode
     VT = Node->getOperand(1).getValueType();
     if (VT == MVT::v8i8) {
       SelectPostStore(Node, 2, AArch64::ST1Twov8b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostStore(Node, 2, AArch64::ST1Twov16b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostStore(Node, 2, AArch64::ST1Twov4h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostStore(Node, 2, AArch64::ST1Twov8h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostStore(Node, 2, AArch64::ST1Twov2s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostStore(Node, 2, AArch64::ST1Twov4s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostStore(Node, 2, AArch64::ST1Twov1d_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostStore(Node, 2, AArch64::ST1Twov2d_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
@@ -3879,28 +3884,28 @@ void AArch64DAGToDAGISel::Select(SDNode
     VT = Node->getOperand(1).getValueType();
     if (VT == MVT::v8i8) {
       SelectPostStore(Node, 3, AArch64::ST1Threev8b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostStore(Node, 3, AArch64::ST1Threev16b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostStore(Node, 3, AArch64::ST1Threev4h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostStore(Node, 3, AArch64::ST1Threev8h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostStore(Node, 3, AArch64::ST1Threev2s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostStore(Node, 3, AArch64::ST1Threev4s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostStore(Node, 3, AArch64::ST1Threev1d_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostStore(Node, 3, AArch64::ST1Threev2d_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
@@ -3908,28 +3913,28 @@ void AArch64DAGToDAGISel::Select(SDNode
     VT = Node->getOperand(1).getValueType();
     if (VT == MVT::v8i8) {
       SelectPostStore(Node, 4, AArch64::ST1Fourv8b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v16i8) {
       SelectPostStore(Node, 4, AArch64::ST1Fourv16b_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i16 || VT == MVT::v4f16) {
       SelectPostStore(Node, 4, AArch64::ST1Fourv4h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v8f16) {
       SelectPostStore(Node, 4, AArch64::ST1Fourv8h_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i32 || VT == MVT::v2f32) {
       SelectPostStore(Node, 4, AArch64::ST1Fourv2s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
       SelectPostStore(Node, 4, AArch64::ST1Fourv4s_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v1i64 || VT == MVT::v1f64) {
       SelectPostStore(Node, 4, AArch64::ST1Fourv1d_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
       SelectPostStore(Node, 4, AArch64::ST1Fourv2d_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
@@ -3937,19 +3942,19 @@ void AArch64DAGToDAGISel::Select(SDNode
     VT = Node->getOperand(1).getValueType();
     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
       SelectPostStoreLane(Node, 2, AArch64::ST2i8_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                VT == MVT::v8f16) {
       SelectPostStoreLane(Node, 2, AArch64::ST2i16_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                VT == MVT::v2f32) {
       SelectPostStoreLane(Node, 2, AArch64::ST2i32_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                VT == MVT::v1f64) {
       SelectPostStoreLane(Node, 2, AArch64::ST2i64_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
@@ -3957,19 +3962,19 @@ void AArch64DAGToDAGISel::Select(SDNode
     VT = Node->getOperand(1).getValueType();
     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
       SelectPostStoreLane(Node, 3, AArch64::ST3i8_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                VT == MVT::v8f16) {
       SelectPostStoreLane(Node, 3, AArch64::ST3i16_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                VT == MVT::v2f32) {
       SelectPostStoreLane(Node, 3, AArch64::ST3i32_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                VT == MVT::v1f64) {
       SelectPostStoreLane(Node, 3, AArch64::ST3i64_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }
@@ -3977,19 +3982,19 @@ void AArch64DAGToDAGISel::Select(SDNode
     VT = Node->getOperand(1).getValueType();
     if (VT == MVT::v16i8 || VT == MVT::v8i8) {
       SelectPostStoreLane(Node, 4, AArch64::ST4i8_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 ||
                VT == MVT::v8f16) {
       SelectPostStoreLane(Node, 4, AArch64::ST4i16_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
                VT == MVT::v2f32) {
       SelectPostStoreLane(Node, 4, AArch64::ST4i32_POST);
-      return;
+      ReturnSelected(Node);
     } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
                VT == MVT::v1f64) {
       SelectPostStoreLane(Node, 4, AArch64::ST4i64_POST);
-      return;
+      ReturnSelected(Node);
     }
     break;
   }




More information about the llvm-commits mailing list