[PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin added a comment.

If SU(i) uses register produced by SI(j):

SU(i) has a predecessor data edge with a number of register produced by SU(j)
SU(j) has a successor data edge with a number of register used by SU(i)

Except that data edges doesn't contain lanemask, but I think this can be solved.

This way SU(i) has predecessor data edges for all used registers in that SU, and SU(j) has successor data edges for every SU using SU(j)'s output.

In https://reviews.llvm.org/D31124#715528, @axeldavy wrote:

> Yes, that could work.
>  I didn't think of that.
>
> Can we rely on having these properties:
>  . If SU(i) relies on the register produced by SU(j), there is a data dependency (even if SU(i) depends on SU(k), which depends itself on SU(j), in other words, redundancies are not removed).
>  . A data dependency between SU(j) and SU(i) always means that SU(i) needs as input the output of SU(j).
>
> To sum up, do we have equivalence between "SU(i) has data dependency with SU(j)" and "one of SU(i) inputs is SU(j) output"
>
> If we have these, I think we can make it work.
>
> In https://reviews.llvm.org/D31124#715515, @vpykhtin wrote:
>
> > I may miss something, but it looks that you can build data edges when building a superdag consisting of blocks. Incoming data edges would be liveins, outcoming - liveouts.
>





Repository:
  rL LLVM

https://reviews.llvm.org/D31124