[PATCH] D31331: [mips][msa] Truncation of vector elements for instructions creating ISD::SHL, ISD::SRL or ISD::SRA nodes

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

You basically need to pattern-match the ISD::AND+ISD::SHL to the appropriate native instruction.  Given that the AND mask is going to get lowered to a constant-pool load (I think?), it's tricky to match with TableGen patterns; probably easiest to add a target-specific MIPSISD::VSHL etc. which masks the shift amount.  The x86 backend does something similar.


https://reviews.llvm.org/D31331