[PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

[Axel Davy via Phabricator via llvm-commits]

axeldavy added a comment.

The assert you have is in CodeGen/RegisterPressure.cpp: void decreaseSetPressure

This call can be from only three locations:
. in SIScheduleBlock::initRegPressure, when we initialize block liveins and liveouts for a given Block.
. In SIScheduleBlock::schedule, when we compute the register usage inside a block with the scheduled order inside the Block.
. outside sisched

If outside sisched, it means we have given an invalid schedule.
For the first two cases, it likely means we have done something wrong when changing the order of the SUs, and thus that handleMove and adjustLaneLiveness wouldn't be enough.

In https://reviews.llvm.org/D31124#715398, @vpykhtin wrote:

> I didn't debugged it and I don't know why you decided so.
>
> In https://reviews.llvm.org/D31124#715389, @axeldavy wrote:
>
> > This would indicate that handleMove + adjustLaneLiveness is insufficient. Do you have any ideas about what is missing ?
>





Repository:
  rL LLVM

https://reviews.llvm.org/D31124