[PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

[Axel Davy via Phabricator via llvm-commits]

axeldavy added a comment.

This would indicate that handleMove + adjustLaneLiveness is insufficient. Do you have any ideas about what is missing ?

In https://reviews.llvm.org/D31124#715170, @vpykhtin wrote:

> I ran lit tests with sished with ShouldTrackLaneMasks=true enabled by default with this patch, the following tests asserted:
>
>   ******************** TEST 'LLVM :: CodeGen/AMDGPU/fceil64.ll' FAILED ********************
>   llc: /srv/vpykhtin/git/llvm/lib/CodeGen/RegisterPressure.cpp:74: void decreaseSetPressure(std::vector<unsigned int>&, const llvm::MachineRegisterInfo&, unsigned int, llvm::LaneBitmask, llvm::LaneBitmask): Assertion `CurrSetPressure[*PSetI] >= Weight && "register pressure underflow"' failed.
>   ******************** TEST 'LLVM :: CodeGen/AMDGPU/fp_to_sint.f64.ll' FAILED ********************
>   llc: /srv/vpykhtin/git/llvm/lib/CodeGen/RegisterPressure.cpp:74: void decreaseSetPressure(std::vector<unsigned int>&, const llvm::MachineRegisterInfo&, unsigned int, llvm::LaneBitmask, llvm::LaneBitmask): Assertion `CurrSetPressure[*PSetI] >= Weight && "register pressure underflow"' failed.
>   ******************** TEST 'LLVM :: CodeGen/AMDGPU/fp_to_uint.f64.ll' FAILED ********************
>   llc: /srv/vpykhtin/git/llvm/lib/CodeGen/RegisterPressure.cpp:74: void decreaseSetPressure(std::vector<unsigned int>&, const llvm::MachineRegisterInfo&, unsigned int, llvm::LaneBitmask, llvm::LaneBitmask): Assertion `CurrSetPressure[*PSetI] >= Weight && "register pressure underflow"' failed.
>   ******************** TEST 'LLVM :: CodeGen/AMDGPU/srem.ll' FAILED ********************
>   llc: /srv/vpykhtin/git/llvm/lib/CodeGen/RegisterPressure.cpp:74: void decreaseSetPressure(std::vector<unsigned int>&, const llvm::MachineRegisterInfo&, unsigned int, llvm::LaneBitmask, llvm::LaneBitmask): Assertion `CurrSetPressure[*PSetI] >= Weight && "register pressure underflow"' failed.
>   ******************** TEST 'LLVM :: CodeGen/AMDGPU/urem.ll' FAILED ********************
>   llc: /srv/vpykhtin/git/llvm/lib/CodeGen/RegisterPressure.cpp:74: void decreaseSetPressure(std::vector<unsigned int>&, const llvm::MachineRegisterInfo&, unsigned int, llvm::LaneBitmask, llvm::LaneBitmask): Assertion `CurrSetPressure[*PSetI] >= Weight && "register pressure underflow"' failed.
>  
>  
>
>
> I enabled sisched by commenting out the following line:
>
>   ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
>     MachineSchedContext *C) const {
>     const SISubtarget &ST = C->MF->getSubtarget<SISubtarget>();
>     //if (ST.enableSIScheduler())
>       return createSIMachineScheduler(C);
>     return createGCNMaxOccupancyMachineScheduler(C);
>   }
>





Repository:
  rL LLVM

https://reviews.llvm.org/D31124