[PATCH] D30539: [tablegen][globalisel] Add support for nested instruction matching.

[Diana Picus via Phabricator via llvm-commits]

rovka added inline comments.


================
Comment at: lib/Target/AArch64/AArch64InstructionSelector.cpp:938
   case TargetOpcode::G_ZEXT:
   case TargetOpcode::G_SEXT: {
     unsigned Opcode = I.getOpcode();
----------------
Aren't these handled by TableGen now?


================
Comment at: test/CodeGen/AArch64/GlobalISel/select-xor.mir:1
-# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=aarch64-linux-gnu -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
----------------
Why is this change necessary?


================
Comment at: utils/TableGen/GlobalISelEmitter.cpp:289
+  /// Only InstructionOperandMatcher needs to do anything for this method.
+  virtual void emitCxxCaptureStmtsForOperand(raw_ostream &OS, RuleMatcher &Rule,
+                                             StringRef Expr) const {}
----------------
Any reason why this needs to be [...]ForOperand instead of just emitCxxCaptureStmts?


================
Comment at: utils/TableGen/GlobalISelEmitter.cpp:655
   /// TODO: When nested instruction matching is implemented, this function will
   ///       descend into the operands and capture variables.
   void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule, StringRef Expr) {
----------------
This TODO should be obsolete now.


https://reviews.llvm.org/D30539