[llvm] r299220 - [SystemZ] Make sure of correct regclasses in insertSelect()

[Jonas Paulsson via llvm-commits]

Author: jonpa
Date: Fri Mar 31 09:06:59 2017
New Revision: 299220

URL: http://llvm.org/viewvc/llvm-project?rev=299220&view=rev
Log:
[SystemZ]  Make sure of correct regclasses in insertSelect()

Since LOCR only accepts GR32 virtual registers, its operands must be copied
into this regclass in insertSelect(), when an LOCR is built. Otherwise, the
case where the source operand was GRX32 will produce invalid IR.

Review: Ulrich Weigand

Added:
    llvm/trunk/test/CodeGen/SystemZ/locr-legal-regclass.ll
Modified:
    llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp

Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=299220&r1=299219&r2=299220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Fri Mar 31 09:06:59 2017
@@ -679,6 +679,12 @@ void SystemZInstrInfo::insertSelect(Mach
     else {
       Opc = SystemZ::LOCR;
       MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
+      unsigned TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
+      unsigned FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
+      BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
+      BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
+      TrueReg = TReg;
+      FalseReg = FReg;
     }
   } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC))
     Opc = SystemZ::LOCGR;

Added: llvm/trunk/test/CodeGen/SystemZ/locr-legal-regclass.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/locr-legal-regclass.ll?rev=299220&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/locr-legal-regclass.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/locr-legal-regclass.ll Fri Mar 31 09:06:59 2017
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 -verify-machineinstrs | FileCheck %s
+;
+; Test that early if conversion produces LOCR with operands of the right
+; register classes.
+
+define void @autogen_SD4739(i8*) {
+; CHECK-NOT: Expected a GR32Bit register, but got a GRX32Bit register
+BB:
+  %L34 = load i8, i8* %0
+  %Cmp56 = icmp sgt i8 undef, %L34
+  br label %CF246
+
+CF246:                                            ; preds = %CF246, %BB
+  %Sl163 = select i1 %Cmp56, i8 %L34, i8 undef
+  br i1 undef, label %CF246, label %CF248
+
+CF248:                                            ; preds = %CF248, %CF246
+  store i8 %Sl163, i8* %0
+  br label %CF248
+}