[PATCH] D31512: Allow targets to opt-in to codegen in SCC order

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
Herald added subscribers: tpr, wdng.

Decouple this setting from EnableIRPA.

     

To support function calls on AMDGPU, it is necessary to
report the global register usage throughout the kernel's
call graph, so callees need to be handled first.


https://reviews.llvm.org/D31512

Files:
  include/llvm/Target/TargetMachine.h
  lib/CodeGen/TargetPassConfig.cpp


Index: lib/CodeGen/TargetPassConfig.cpp
===================================================================
--- lib/CodeGen/TargetPassConfig.cpp
+++ lib/CodeGen/TargetPassConfig.cpp
@@ -534,7 +534,7 @@
   addPreISel();
 
   // Force codegen to run according to the callgraph.
-  if (TM->Options.EnableIPRA)
+  if (TM->requiresCodeGenSCCOrder())
     addPass(new DummyCGSCCPass);
 
   // Add both the safe stack and the stack protection passes: each of them will
Index: include/llvm/Target/TargetMachine.h
===================================================================
--- include/llvm/Target/TargetMachine.h
+++ include/llvm/Target/TargetMachine.h
@@ -89,6 +89,7 @@
   const MCSubtargetInfo *STI;
 
   unsigned RequireStructuredCFG : 1;
+  unsigned RequireCodeGenSCCOrder : 1;
   unsigned O0WantsFastISel : 1;
 
 public:
@@ -158,6 +159,9 @@
   bool requiresStructuredCFG() const { return RequireStructuredCFG; }
   void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
 
+  bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
+  void setRequiresCodeGenSCCOrder(bool Value) { RequireCodeGenSCCOrder = Value; }
+
   /// Returns the code generation relocation model. The choices are static, PIC,
   /// and dynamic-no-pic, and target default.
   Reloc::Model getRelocationModel() const;


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