[PATCH] D31483: [DAGCombiner] convert and-of-seteq to bitwise logic+seteq (PR32401)

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
Herald added a subscriber: mcrosier.

This is a generic combine to reduce icmp logic as discussed in:
https://bugs.llvm.org/show_bug.cgi?id=32401

I think these are all wins for targets in the affected tests, but a target could reverse this if it is not a win (or we can add a target hook to selectively disable this). A follow-up would allow us to canonicalize IR to the icmp form in instcombine.

I had initially enabled this for vectors too, but there were several regressions because of the scalar-limited constant matching in the combines above this one (and likely we're accidentally excluding vectors from folds that would reduce to those forms).


https://reviews.llvm.org/D31483

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/and-setcc.ll
  test/CodeGen/PowerPC/and-setcc.ll
  test/CodeGen/X86/and-setcc.ll
  test/CodeGen/X86/avx512-cmp.ll

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