[llvm] r299034 - [CodeGen] clean up and add tests for scalar and-of-setcc; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 29 14:58:53 PDT 2017
Author: spatel
Date: Wed Mar 29 16:58:52 2017
New Revision: 299034
URL: http://llvm.org/viewvc/llvm-project?rev=299034&view=rev
Log:
[CodeGen] clean up and add tests for scalar and-of-setcc; NFC
https://bugs.llvm.org/show_bug.cgi?id=32401
Added:
llvm/trunk/test/CodeGen/ARM/and-setcc.ll
- copied, changed from r299033, llvm/trunk/test/CodeGen/ARM/setcc-sentinals.ll
llvm/trunk/test/CodeGen/PowerPC/and-setcc.ll
llvm/trunk/test/CodeGen/X86/and-setcc.ll
- copied, changed from r299033, llvm/trunk/test/CodeGen/X86/setcc-sentinals.ll
Removed:
llvm/trunk/test/CodeGen/ARM/setcc-sentinals.ll
llvm/trunk/test/CodeGen/X86/setcc-sentinals.ll
Copied: llvm/trunk/test/CodeGen/ARM/and-setcc.ll (from r299033, llvm/trunk/test/CodeGen/ARM/setcc-sentinals.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/and-setcc.ll?p2=llvm/trunk/test/CodeGen/ARM/and-setcc.ll&p1=llvm/trunk/test/CodeGen/ARM/setcc-sentinals.ll&r1=299033&r2=299034&rev=299034&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/setcc-sentinals.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/and-setcc.ll Wed Mar 29 16:58:52 2017
@@ -1,14 +1,36 @@
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -asm-verbose=false %s -o - | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s
-define zeroext i1 @test0(i32 %x) nounwind {
-; CHECK-LABEL: test0:
-; CHECK: add [[REG:(r[0-9]+)|(lr)]], r0, #1
-; CHECK-NEXT: mov r0, #0
-; CHECK-NEXT: cmp [[REG]], #1
-; CHECK-NEXT: movwhi r0, #1
-; CHECK-NEXT: bx lr
+define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind {
+; CHECK-LABEL: ne_neg1_and_ne_zero:
+; CHECK: @ BB#0:
+; CHECK-NEXT: add r1, r0, #1
+; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: cmp r1, #1
+; CHECK-NEXT: movwhi r0, #1
+; CHECK-NEXT: bx lr
%cmp1 = icmp ne i32 %x, -1
- %not.cmp = icmp ne i32 %x, 0
- %.cmp1 = and i1 %cmp1, %not.cmp
- ret i1 %.cmp1
+ %cmp2 = icmp ne i32 %x, 0
+ %and = and i1 %cmp1, %cmp2
+ ret i1 %and
}
+
+; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
+
+define zeroext i1 @cmpeq_logical(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; CHECK-LABEL: cmpeq_logical:
+; CHECK: @ BB#0:
+; CHECK-NEXT: cmp r2, r3
+; CHECK-NEXT: mov r2, #0
+; CHECK-NEXT: movweq r2, #1
+; CHECK-NEXT: mov r12, #0
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: movweq r12, #1
+; CHECK-NEXT: and r0, r12, r2
+; CHECK-NEXT: bx lr
+ %cmp1 = icmp eq i32 %a, %b
+ %cmp2 = icmp eq i32 %c, %d
+ %and = and i1 %cmp1, %cmp2
+ ret i1 %and
+}
+
Removed: llvm/trunk/test/CodeGen/ARM/setcc-sentinals.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/setcc-sentinals.ll?rev=299033&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/setcc-sentinals.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/setcc-sentinals.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -asm-verbose=false %s -o - | FileCheck %s
-
-define zeroext i1 @test0(i32 %x) nounwind {
-; CHECK-LABEL: test0:
-; CHECK: add [[REG:(r[0-9]+)|(lr)]], r0, #1
-; CHECK-NEXT: mov r0, #0
-; CHECK-NEXT: cmp [[REG]], #1
-; CHECK-NEXT: movwhi r0, #1
-; CHECK-NEXT: bx lr
- %cmp1 = icmp ne i32 %x, -1
- %not.cmp = icmp ne i32 %x, 0
- %.cmp1 = and i1 %cmp1, %not.cmp
- ret i1 %.cmp1
-}
Added: llvm/trunk/test/CodeGen/PowerPC/and-setcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/and-setcc.ll?rev=299034&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/and-setcc.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/and-setcc.ll Wed Mar 29 16:58:52 2017
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs | FileCheck %s
+
+define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
+; CHECK-LABEL: ne_neg1_and_ne_zero:
+; CHECK: # BB#0:
+; CHECK-NEXT: addi 3, 3, 1
+; CHECK-NEXT: li 4, 0
+; CHECK-NEXT: li 12, 1
+; CHECK-NEXT: cmpldi 3, 1
+; CHECK-NEXT: isel 3, 12, 4, 1
+; CHECK-NEXT: blr
+ %cmp1 = icmp ne i64 %x, -1
+ %cmp2 = icmp ne i64 %x, 0
+ %and = and i1 %cmp1, %cmp2
+ ret i1 %and
+}
+
+; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
+
+define zeroext i1 @cmpeq_logical(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
+; CHECK-LABEL: cmpeq_logical:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpw 0, 3, 4
+; CHECK-NEXT: cmpw 1, 5, 6
+; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: crnand 20, 2, 6
+; CHECK-NEXT: isel 3, 0, 3, 20
+; CHECK-NEXT: blr
+ %cmp1 = icmp eq i16 %a, %b
+ %cmp2 = icmp eq i16 %c, %d
+ %and = and i1 %cmp1, %cmp2
+ ret i1 %and
+}
+
Copied: llvm/trunk/test/CodeGen/X86/and-setcc.ll (from r299033, llvm/trunk/test/CodeGen/X86/setcc-sentinals.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/and-setcc.ll?p2=llvm/trunk/test/CodeGen/X86/and-setcc.ll&p1=llvm/trunk/test/CodeGen/X86/setcc-sentinals.ll&r1=299033&r2=299034&rev=299034&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/setcc-sentinals.ll (original)
+++ llvm/trunk/test/CodeGen/X86/and-setcc.ll Wed Mar 29 16:58:52 2017
@@ -1,13 +1,33 @@
-; RUN: llc < %s -mcpu=generic -march=x86-64 -asm-verbose=false | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
-define zeroext i1 @test0(i64 %x) nounwind {
-; CHECK-LABEL: test0:
-; CHECK-NEXT: incq %[[X:rdi|rcx]]
-; CHECK-NEXT: cmpq $1, %[[X]]
-; CHECK-NEXT: seta %al
-; CHECK-NEXT: ret
+define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) nounwind {
+; CHECK-LABEL: ne_neg1_and_ne_zero:
+; CHECK: # BB#0:
+; CHECK-NEXT: incq %rdi
+; CHECK-NEXT: cmpq $1, %rdi
+; CHECK-NEXT: seta %al
+; CHECK-NEXT: retq
%cmp1 = icmp ne i64 %x, -1
- %not.cmp = icmp ne i64 %x, 0
- %.cmp1 = and i1 %cmp1, %not.cmp
- ret i1 %.cmp1
+ %cmp2 = icmp ne i64 %x, 0
+ %and = and i1 %cmp1, %cmp2
+ ret i1 %and
}
+
+; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
+
+define zeroext i1 @cmpeq_logical(i8 %a, i8 %b, i8 %c, i8 %d) nounwind {
+; CHECK-LABEL: cmpeq_logical:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpb %sil, %dil
+; CHECK-NEXT: sete %sil
+; CHECK-NEXT: cmpb %cl, %dl
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: andb %sil, %al
+; CHECK-NEXT: retq
+ %cmp1 = icmp eq i8 %a, %b
+ %cmp2 = icmp eq i8 %c, %d
+ %and = and i1 %cmp1, %cmp2
+ ret i1 %and
+}
+
Removed: llvm/trunk/test/CodeGen/X86/setcc-sentinals.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc-sentinals.ll?rev=299033&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/setcc-sentinals.ll (original)
+++ llvm/trunk/test/CodeGen/X86/setcc-sentinals.ll (removed)
@@ -1,13 +0,0 @@
-; RUN: llc < %s -mcpu=generic -march=x86-64 -asm-verbose=false | FileCheck %s
-
-define zeroext i1 @test0(i64 %x) nounwind {
-; CHECK-LABEL: test0:
-; CHECK-NEXT: incq %[[X:rdi|rcx]]
-; CHECK-NEXT: cmpq $1, %[[X]]
-; CHECK-NEXT: seta %al
-; CHECK-NEXT: ret
- %cmp1 = icmp ne i64 %x, -1
- %not.cmp = icmp ne i64 %x, 0
- %.cmp1 = and i1 %cmp1, %not.cmp
- ret i1 %.cmp1
-}
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